arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2307.04443cs.CVcs.LG
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搜索时高效的设备约束感知神经架构搜索

Search-time Efficient Device Constraints-Aware Neural Architecture Search

Indian Institute of Technology(印度理工学院)

Oshin Dutta, Tanu Kanvar, Sumeet Agarwal

AI总结:

本文提出 DCA-NAS,一种融合模型大小和浮点运算约束的快速神经架构搜索方法,通过权重共享与通道瓶颈加速搜索,在多个图像分类数据集和设备专用基准上取得优于手工架构或最先进的性能。

摘要:

边缘计算旨在使物联网设备等边缘设备能够在本地处理数据,而无需依赖云端。然而,计算机视觉和自然语言处理等深度学习技术可能计算开销大且内存密集。由于不同设备的内存和计算约束各不相同,为每台设备手工设计专用架构并不现实。为解决这些问题,我们通过神经架构搜索(NAS)自动构建针对设备约束优化的任务专用深度学习架构。我们提出 DCA-NAS,这是一种有原则的快速神经网络架构搜索方法,融合了模型大小和浮点运算次数等边缘设备约束。该方法采用权重共享和通道瓶颈技术来加快搜索时间。基于我们的实验,我们发现 DCA-NAS 在相似规模的模型上优于手工设计的架构,并且在 CIFAR-10、CIFAR-100 和 Imagenet-1k 等各种图像分类数据集上可与流行的移动端架构相媲美。在 DARTS 和 NAS-Bench-201 搜索空间上的实验展示了 DCA-NAS 的泛化能力。进一步在 Hardware-NAS-Bench 上评估我们的方法时,发现了具有低推理延迟和最先进性能的设备专用架构。

英文摘要:

Edge computing aims to enable edge devices, such as IoT devices, to process data locally instead of relying on the cloud. However, deep learning techniques like computer vision and natural language processing can be computationally expensive and memory-intensive. Creating manual architectures specialized for each device is infeasible due to their varying memory and computational constraints. To address these concerns, we automate the construction of task-specific deep learning architectures optimized for device constraints through Neural Architecture Search (NAS). We present DCA-NAS, a principled method of fast neural network architecture search that incorporates edge-device constraints such as model size and floating-point operations. It incorporates weight sharing and channel bottleneck techniques to speed up the search time. Based on our experiments, we see that DCA-NAS outperforms manual architectures for similar sized models and is comparable to popular mobile architectures on various image classification datasets like CIFAR-10, CIFAR-100, and Imagenet-1k. Experiments with search spaces -- DARTS and NAS-Bench-201 show the generalization capabilities of DCA-NAS. On further evaluating our approach on Hardware-NAS-Bench, device-specific architectures with low inference latency and state-of-the-art performance were discovered.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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