Image processing algorithms are prime targets for hardware acceleration as they are commonly used in resource- and power-limited applications. Today's image processing accelerator designs make rigid assumptions about the algorithm structures and/or on-chip memory resources. As a result, they either have narrow applicability or result in inefficient designs.
This paper presents a compiler framework that automatically generates memory- and power-efficient image processing accelerators. We allow programmers to describe generic image processing algorithms (in a domain specific language) and specify on-chip memory structures available. Our framework then formulates a constrained optimization problem that minimizes on-chip memory usage while maintaining theoretical maximum throughput. The key challenge we address is to analytically express the throughput bottleneck, on-chip memory contention, to enable a lightweight compilation. FPGA prototyping and ASIC synthesis show that, compared to existing approaches, accelerators generated by our framework reduce the on-chip memory usage and/or power consumption by double digits.
A Low-Power Sparse Convolution Accelerator with Idle-First-Task-Assignment for Edge Vision
TUD Dresden University of Technology（德累斯顿工业大学）；Center for Scalable Data Analytics and Artificial Intelligence (ScaDS.AI Dresden)（可扩展数据分析与人工智能中心）；Centre for Tactile Internet with Human-in-the-loop (CeTI)（人机交互触觉互联网中心）
TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
Eindhoven University of Technology（埃因霍温理工大学）；University of California, Los Angeles（加州大学洛杉矶分校）；Chinese University of Hong Kong（香港中文大学）；University of Massachusetts Amherst（马萨诸塞大学阿默斯特分校）
STISA: A 0.16 GOPS/W/PE Single-Shot Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design
Zhejiang University-University of Illinois Urbana-Champaign Institute, Zhejiang University（浙江大学伊利诺伊大学厄巴纳香槟校区联合学院，浙江大学）；Singapore University of Technology and Design（新加坡科技设计大学）
Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator
Imperial College London（帝国理工学院）；University College London（伦敦大学学院）；University of Cambridge（剑桥大学）；Hunan Normal University（湖南师范大学）；Corerain Technologies Ltd.（科瑞斯科技有限公司）
