分层记忆：用局域门模拟量子LDPC码
Hierarchical memories: Simulating quantum LDPC codes with local gates
AI总结：
本文提出分层码族，通过将恒定码率量子LDPC码与表面码级联，在二维最近邻门约束下实现高效容错量子记忆，并证明其在保守假设下优于纯表面码编码方案。
摘要：
恒定码率的低密度奇偶校验（LDPC）码是构建高效容错量子记忆的有前景的候选方案。然而，如果物理门受到几何局域性约束，实现这些码就变得具有挑战性。在本文中，我们构造了一个新的 $[[N,K,D]]$ 码族，称为分层码（hierarchical codes），它编码的逻辑量子比特数为 $K = Ω(N/\log(N)^2)$。该码族的第 N 个元素通过将一个恒定码率量子LDPC码与一个表面码（surface code）级联而获得；二维中的最近邻门足以实现相应的错误症状提取电路并达到阈值。在阈值以下，逻辑失败率作为距离 $D(N)$ 的函数以超多项式速度消失。我们提出了一种用于实现错误症状提取电路的双层架构，并估计了该架构的逻辑失败率。在保守假设下，我们发现分层码优于将所有逻辑量子比特都编码在表面码中的基本编码方案。
英文摘要：
Constant-rate low-density parity-check (LDPC) codes are promising candidates for constructing efficient fault-tolerant quantum memories. However, if physical gates are subject to geometric-locality constraints, it becomes challenging to realize these codes. In this paper, we construct a new family of $[[N,K,D]]$ codes, referred to as hierarchical codes, that encode a number of logical qubits $K = Ω(N/\log(N)^2)$. The N-th element of this code family is obtained by concatenating a constant-rate quantum LDPC code with a surface code; nearest-neighbor gates in two dimensions are sufficient to implement the corresponding syndrome-extraction circuit and achieve a threshold. Below threshold the logical failure rate vanishes superpolynomially as a function of the distance $D(N)$. We present a bilayer architecture for implementing the syndrome-extraction circuit, and estimate the logical failure rate for this architecture. Under conservative assumptions, we find that the hierarchical code outperforms the basic encoding where all logical qubits are encoded in the surface code.
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