基于误差曲面的VVC分数阶运动估计算法及硬件实现
An Error-Surface-Based Fractional Motion Estimation Algorithm and Hardware Implementation for VVC
摘要：
与其前身高效视频编码（HEVC）相比，通用视频编码（VVC）引入了更多的编码工具来提高压缩效率。对于帧间编码，分数运动估计（FME）仍然具有高计算工作量，这限制了视频编码器的实时处理能力。在此背景下，本文提出了一种基于误差面的FME算法和相应的硬件实现。该算法创建由整数运动矢量（IMV）及其邻居的率失真（R-D）成本构造的误差表面。该方法不需要迭代和插值，从而减少了面积和功耗，提高了硬件的吞吐量。实验结果表明，与LD-P结构的VTM 16.0相比，相应的BDBR损耗仅为0.47%。硬件实现采用GF 28 nm工艺进行综合。它可以支持13种不同大小的CU，从128 x128到8x8不等。在400 MHz时，吞吐量可达4K@30fps，门数为192 k，功耗为12.64mW。在631 MHz时，仅采用四叉树搜索，吞吐量可达8K@30fps。据我们所知，这项工作是第一个硬件架构的VVC有限元与插值自由的战略
英文摘要：
Versatile Video Coding (VVC) introduces more coding tools to improve compression efficiency compared to its predecessor High Efficiency Video Coding (HEVC). For inter-frame coding, Fractional Motion Estimation (FME) still has a high computational effort, which limits the real-time processing capability of the video encoder. In this context, this paper proposes an error-surface-based FME algorithm and the corresponding hardware implementation. The algorithm creates an error surface constructed by the Rate-Distortion (R-D) cost of the integer motion vector (IMV) and its neighbors. This method requires no iteration and interpolation, thus reducing the area and power consumption and increasing the throughput of the hardware. The experimental results show that the corresponding BDBR loss is only 0.47% compared to VTM 16.0 in LD-P configuration. The hardware implementation was synthesized using GF 28nm process. It can support 13 different sizes of CU varying from 128x128 to 8x8. The measured throughput can reach 4K@30fps at 400MHz, with a gate count of 192k and power consumption of 12.64 mW. And the throughput can reach 8K@30fps at 631MHz when only quadtree is searched. To the best of our knowledge, this work is the first hardware architecture for VVC FME with interpolation-free strategies
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