SF-SGL：基于线性测量的无解谱图学习
SF-SGL: Solver-Free Spectral Graph Learning from Linear Measurements
摘要：
这项工作介绍了一个高度可扩展的谱图致密化框架（SGL），用于学习具有线性测量的电阻网络，如节点电压和电流。我们证明了所提出的图学习方法等价于求解具有Laplacian精度矩阵的经典图形Lasso问题。我们证明，给定$O(\log N)$对的电压和电流测量，它是可能的，以恢复稀疏的$N$节点电阻网络，可以很好地保持原始图上的有效电阻距离。此外，学习的图还保留了原始图的结构（频谱）属性，这可能会在许多电路设计和优化任务中得到利用。为了实现更可扩展的性能，我们还引入了一种无求解器方法（SF-SGL），该方法利用图形的多级谱近似，并允许将整个图形谱（待学习）可扩展且灵活地分解为多个不同的特征值簇（频带）。这种无求解器的方法使我们能够更有效地识别最关键的频谱边缘，以减少各种范围的频谱嵌入失真。通过大量的实验，各种现实世界的测试案例，我们表明，所提出的方法是高度可扩展的学习稀疏电阻网络，而不牺牲解决方案的质量。我们还介绍了一种数据驱动的EDA算法，用于无矢量功率/热完整性验证，通过利用几个电压/温度测量值来估计整个芯片的最坏情况下的电压/温度（梯度）分布。
英文摘要：
This work introduces a highly-scalable spectral graph densification framework (SGL) for learning resistor networks with linear measurements, such as node voltages and currents. We show that the proposed graph learning approach is equivalent to solving the classical graphical Lasso problems with Laplacian-like precision matrices. We prove that given $O(\log N)$ pairs of voltage and current measurements, it is possible to recover sparse $N$-node resistor networks that can well preserve the effective resistance distances on the original graph. In addition, the learned graphs also preserve the structural (spectral) properties of the original graph, which can potentially be leveraged in many circuit design and optimization tasks. To achieve more scalable performance, we also introduce a solver-free method (SF-SGL) that exploits multilevel spectral approximation of the graphs and allows for a scalable and flexible decomposition of the entire graph spectrum (to be learned) into multiple different eigenvalue clusters (frequency bands). Such a solver-free approach allows us to more efficiently identify the most spectrally-critical edges for reducing various ranges of spectral embedding distortions. Through extensive experiments for a variety of real-world test cases, we show that the proposed approach is highly scalable for learning sparse resistor networks without sacrificing solution quality. We also introduce a data-driven EDA algorithm for vectorless power/thermal integrity verifications to allow estimating worst-case voltage/temperature (gradient) distributions across the entire chip by leveraging a few voltage/temperature measurements.
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