GraphAGILE：一种面向低延迟 GNN 推理的基于 FPGA 的覆盖加速器
GraphAGILE: An FPGA-based Overlay Accelerator for Low-latency GNN Inference
AI总结：
针对 GNN 推理低延迟需求，提出基于 FPGA 的 GraphAGILE 覆盖架构，通过统一 ISA、ACK 硬件模块及多项编译器优化支持多种 GNN 模型且无需重配置。
摘要：
本文提出 GraphAGILE，这是一种面向图神经网络（GNN）推理的、基于 FPGA 的领域专用覆盖加速器。GraphAGILE 由两部分组成：（1）一种带有指令集的新型统一架构设计；（2）构建于该指令集之上、能够快速生成优化代码的编译器。得益于所提出的指令集架构（ISA）和编译器，GraphAGILE 在对各种 GNN 模型和输入图执行推理时，不需要进行任何 FPGA 重配置。在架构设计方面，我们提出了名为 Adaptive Computation Kernel（ACK，自适应计算内核）的新型硬件模块，它可以执行 GNN 的各种计算内核，包括通用矩阵乘法（GEMM）、稀疏-稠密矩阵乘法（SpDMM）和采样稠密-稠密矩阵乘法（SDDMM）。该编译器接收 GNN 模型的规格说明和图元数据（例如顶点数和边数）作为输入，并生成用于推理执行的指令序列。我们开发了以下编译器优化以降低推理延迟：（1）计算顺序优化，自动对计算图重新排序以降低总计算复杂度；（2）层融合，合并相邻层以减少数据通信量；（3）数据划分，采用以分区为中心的执行方案，对输入图进行划分以适配 FPGA 可用的片上存储器；（4）内核映射，自动为 ACK 选择执行模式，并执行任务调度，使计算与数据通信重叠，实现动态负载均衡。我们在最先进的 FPGA 平台 Xilinx Alveo U250 上实现了 GraphAGILE。GraphAGILE 能够执行广泛使用的 GNN 模型，包括 GCN、GAT、GIN、GraphSAGE、SGC 以及 GraphGym 支持的其他 GNN 模型。
英文摘要：
This paper presents GraphAGILE, a domain-specific FPGA-based overlay accelerator for graph neural network (GNN) inference. GraphAGILE consists of (1) \emph{a novel unified architecture design} with an \emph{instruction set}, and (2) \emph{a compiler} built upon the instruction set that can quickly generate optimized code. Due to the proposed instruction set architecture (ISA) and the compiler, GraphAGILE does not require any FPGA reconfiguration when performing inference on various GNN models and input graphs. For the architecture design, we propose a novel hardware module named Adaptive Computation Kernel (ACK), that can execute various computation kernels of GNNs, including general matrix multiplication (GEMM), sparse-dense matrix multiplication (SpDMM) and sampled dense-dense matrix multiplication (SDDMM). The compiler takes the specifications of a GNN model and the graph meta data (e.g., the number of vertices and edges) as input, and generates a sequence of instructions for inference execution. We develop the following compiler optimizations to reduce inference latency: (1) computation order optimization that automatically reorders the computation graph to reduce the total computation complexity, (2) layer fusion that merges adjacent layers to reduce data communication volume, (3) data partitioning with a partition-centric execution scheme that partitions the input graph to fit the available on-chip memory of FPGA, (4) kernel mapping that automatically selects execution mode for ACK, and performs task scheduling to overlap computation with data communication and achieves dynamic load balance. We implement GraphAGILE on a state-of-the-art FPGA platform, Xilinx Alveo U250. GraphAGILE can execute widely used GNN models, including GCN, GAT, GIN, GraphSAGE, SGC and other GNN models supported by GraphGym.
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