一种用于高速可重构计算电路的多态电光逻辑门
A Polymorphic Electro-Optic Logic Gate for High-Speed Reconfigurable Computing Circuits
摘要：
随着摩尔定律的逐渐消失，集成电光（E-O）计算电路已经显示出革命性的潜力，为计算提供越来越快和更有效的硬件。从文献中计算的E-O电路可以在高比特率下以最小的延迟操作。然而，它们面临的缺点，由于其操作数处理的复杂性，不可摊销的高面积和静态功率开销，以及一般不适合大规模集成的网状限制芯片。为了克服这些缺点，在本文中，我们提出了一种基于微谐振器（MRR）的多态E-O逻辑门（MRR-PEOLG），可以动态编程，以实现不同的逻辑功能在不同的时间。我们的MRR-PEOLG可以提供紧凑性和多态性的E-O电路，从而改善其操作数处理和摊销的面积和静态功耗开销。我们的MRR-PEOLG模型使用光子学代工验证的工具来执行其多态逻辑功能的频域和时域分析。我们的评估表明，使用我们的MRR-PEOLG在两个E-O电路从以前的作品可以减少他们的面积能量延迟产品高达82.6 $\times$。关于我们的MRR-PEOLG建模和仿真的教程以及相关代码和文件可在https://github.com/uky-UCAT/MRR-PEOLG上获得。
英文摘要：
In the wake of dwindling Moore's law, integrated electro-optic (E-O) computing circuits have shown revolutionary potential to provide progressively faster and more efficient hardware for computing. The E-O circuits for computing from the literature can operate with minimal latency at high bit-rates. However, they face shortcomings due to their operand handling complexity, non-amortizable high area and static power overheads, and general unsuitability for large-scale integration on reticle-limited chips. To alleviate these shortcomings, in this paper, we present a microring resonator (MRR) based polymorphic E-O logic gate (MRR-PEOLG) that can be dynamically programmed to implement different logic functions at different times. Our MRR-PEOLG can provide compactness and polymorphism to E-O circuits, to consequently improve their operand handling and amortization of area and static power overheads. We model our MRR-PEOLG using photonics foundry-validated tools to perform frequency and time-domain analysis of its polymorphic logic functions. Our evaluation shows that the use of our MRR-PEOLG in two E-O circuits from prior works can reduce their area-energy-delay product by up to 82.6$\times$. A tutorial on the modeling and simulation of our MRR-PEOLG, along with related codes and files, is available on https://github.com/uky-UCAT/MRR-PEOLG.
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