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arXiv 2212.05397eess.SYcs.SY
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基于现代异构FPGA的部分动态可重构系统任务模块划分、调度与布图规划

Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs

Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen, Yi Kang

摘要:

现代现场可编程门阵列(FPGA)可以部分地动态可重构与异构资源分布在芯片上。而基于FPGA的部分动态可重构系统(FPGA-PDRS)可以用来加速计算,提高计算的灵活性。然而,传统的FPGA-PDRS设计是基于手工设计。实现FPGA-PDRS的自动化需要解决异构资源上的任务模块划分、调度和布图规划等问题。现有的工作只是部分地解决了FPGA-PDRS的自动化过程或为FPGA-PDRS建立同构资源模型的问题。为了更好地解决FPGA-PDRS自动化过程中存在的问题,缩小算法与应用之间的差距,本文提出了一个完整的工作流程,包括根据资源需求生成任务模块候选形状列表的预处理过程,搜索任务模块划分、调度和布图规划的解决方案的探索过程,以及后优化以提高布图规划的成功率。实验结果表明,与现有工作流相比,该完整工作流在提高片上异构资源重用率的同时,性能平均提高了18.7%,通信开销平均降低了8.6%.基于探测过程产生的解,后优化可以使布图规划的成功率提高14%.

英文摘要:

Modern field programmable gate array(FPGA) can be partially dynamically reconfigurable with heterogeneous resources distributed on the chip. And FPGA-based partially dynamically reconfigurable system(FPGA-PDRS) can be used to accelerate computing and improve computing flexibility. However, the traditional design of FPGA-PDRS is based on manual design. Implementing the automation of FPGA-PDRS needs to solve the problems of task modules partitioning, scheduling, and floorplanning on heterogeneous resources. Existing works only partly solve problems for the automation process of FPGA-PDRS or model homogeneous resource for FPGA-PDRS. To better solve the problems in the automation process of FPGA-PDRS and narrow the gap between algorithm and application, in this paper, we propose a complete workflow including three parts, pre-processing to generate the list of task modules candidate shapes according to the resources requirements, exploration process to search the solution of task modules partitioning, scheduling, and floorplanning, and post-optimization to improve the success rate of floorplan. Experimental results show that, compared with state-of-the-art work, the proposed complete workflow can improve performance by 18.7\%, reduce communication cost by 8.6\%, on average, with improving the resources reuse rate of the heterogeneous resources on the chip. And based on the solution generated by the exploration process, the post-optimization can improve the success rate of the floorplan by 14\%.

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