在可扩展的RISC-V众核处理器上实现PUSCH的高效并行化
Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor
摘要：
5G无线电接入网络分解和软件化在计算性能方面对处理单元提出了挑战。在物理层级别，基带处理计算工作通常被卸载到专用硬件加速器。然而，软件定义的无线电接入网络的趋势需要灵活的，可编程的架构。在本文中，我们探讨了软件设计，并行化和优化的物理上行链路共享信道（PUSCH）接收MemPool和TeraPool，两个众核系统分别具有256和1024个小型和高效的RISC-V内核与大型共享L1数据存储器的低物理层（PHY）的关键内核。PUSCH处理要求高且严格受时间约束，它代表了对基带处理器的挑战，并且它对于大多数上行链路信道也是常见的。因此，我们的分析推广到gNodeB（gNB）处的上行链路接收器的整个较低PHY。基于PUSCH算法阶段所需的计算工作量的评估（在乘-累加操作中），我们专注于主导内核的并行实现，即快速傅立叶变换，矩阵-矩阵乘法和矩阵分解内核，用于线性系统的解决方案。我们优化的并行内核分别在MemPool和TeraPool上实现了211，225，158和762，880，722的加速比，高利用率（0.81，0.89，0.71和0.74，0.88，0.71），可与单核串行执行相媲美，向全软件PUSCH实现迈进了一步。
英文摘要：
5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband processing computational effort is typically offloaded to specialized hardware accelerators. However, the trend toward software-defined radio-access networks demands flexible, programmable architectures. In this paper, we explore the software design, parallelization and optimization of the key kernels of the lower physical layer (PHY) for physical uplink shared channel (PUSCH) reception on MemPool and TeraPool, two manycore systems having respectively 256 and 1024 small and efficient RISC-V cores with a large shared L1 data memory. PUSCH processing is demanding and strictly time-constrained, it represents a challenge for the baseband processors, and it is also common to most of the uplink channels. Our analysis thus generalizes to the entire lower PHY of the uplink receiver at gNodeB (gNB). Based on the evaluation of the computational effort (in multiply-accumulate operations) required by the PUSCH algorithmic stages, we focus on the parallel implementation of the dominant kernels, namely fast Fourier transform, matrix-matrix multiplication, and matrix decomposition kernels for the solution of linear systems. Our optimized parallel kernels achieve respectively on MemPool and TeraPool speedups of 211, 225, 158, and 762, 880, 722, at high utilization (0.81, 0.89, 0.71, and 0.74, 0.88, 0.71), comparable a single-core serial execution, moving a step closer toward a full-software PUSCH implementation.
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