基于强臂动态锁存器的SAR-ADC高速低功耗低失调比较器设计
Design of a Strong-Arm Dynamic-Latch based comparator with high speed, low power and low offset for SAR-ADC
摘要：
奈奎斯特速率和过采样模数转换器（ADC）利用比较器来完成量化和采样。因此，比较器对ADC的速度和精度有很大影响。这项研究提供了一个基于动态锁存器的比较器，实现了最低的延迟，最大面积效率的实现，降低功耗和低失调的修改后的设计。该电路采用GDPK 45 nm标准CMOS工艺设计和仿真，工作在100 MHz时钟，1.2V电源电压。使用CADENCE Virtuoso EDA工具进行了设计和仿真。与原始设计相比，PDP很容易减少约6%，失调电压降低了8 mV，而无需权衡速度。
英文摘要：
Comparators are utilised by Nyquist-rate and oversampling analog to digital converters (ADCs) to accomplish quantization and perhaps sampling. Thus, comparators have a substantial effect on the speed and accuracy of ADCs. This study provides a revised design for a dynamic-latch-based comparator that achieves the lowest latency, maximum area-efficient realisation, reduced power dissipation, and low offset. The proposed circuit has been designed and simulated using GDPK 45 nm standard CMOS-Process to operate on 100 MHz clock, at 1.2V supply voltage. Design and simulation have been carried out using CADENCE Virtuoso EDA tool. Compared to the original design, the PDP was easily reduced by approximately by 6% with offset voltage reduced by 8 mV without speed trade-off.
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