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arXiv 2204.12913cs.SE
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依赖系统的形式化验证方法综述

A Survey on Formal Verification Approaches for Dependable Systems

Fayhaa Hameedi Khlaif, Shawkat Sabah Khairullah

摘要:

在工业自动化、过程控制、交通运输和医疗数字设备等不同的安全关键应用中,数字嵌入式系统的复杂性一直在增加。这些系统的正确操作过于依赖于嵌入式数字设备的行为。因此,在嵌入式设备的设计阶段所犯的任何错误或错误都可能改变关键系统的整体功能并导致灾难性后果。为了检测这些误差并消除它们对系统的影响,必须创新新的误差检测方法,并将其应用于数字系统的设计中。然而,这些方法需要巨大的成本和时间。用于解决此问题的方法之一称为验证与确认(V&V),它在进入实施阶段之前,在开发过程的早期确认系统行为满足需求。由于它们在复杂数字系统构建中的优势和重要性,形式V&V方法的应用最近引起了人们的广泛关注。本文重点介绍了各种形式化验证方法的研究,以及如何实现V&V,以开发高可靠的数字嵌入式系统

英文摘要:

The complexity of digital embedded systems has been increasing in different safety-critical applications such as industrial automation, process control, transportation, and medical digital devices. The correct operation of these systems relies too heavily on the behavior of the embedded digital device. As a result, any mistake or error made during the design stage of the embedded device can change the overall functionality of the critical system and cause catastrophic consequences. To detect these errors and eliminate their effects on the system, new error detection approaches must be innovated and used in the design of the digital system. However, these methods require enormous costs and time. One of these methods being employed to solve this issue is called Verification and Validation (V&V) which confirms that the system behavior meets the requirements early in the development process, before moving on to the implementation phase. Because of their benefits and importance in the building of complex digital systems, the employment of formal V&V methods has recently attracted a lot of attention. This paper focuses on presenting various studies on formal verification approaches and how the V&V can be achieved for developing high dependable digital embedded systems

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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