AgileWatts：面向延迟敏感型服务器应用的高能效CPU核空闲状态架构
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications
AI总结：
AgileWatts通过电源门控、上下文保留、缓存睡眠模式和ADPLL等创新，大幅降低延迟敏感型服务器应用在深度空闲状态下的能耗，同时保持极低性能损失。
摘要：
现代数据中心中运行的用户面向型应用表现出不规则请求模式，并由众多具有严格延迟要求的服务实现。这些特性使得当处理器空闲时，由于从深度空闲电源状态（C状态）转换时间过长，现有节能技术效果不佳。虽然先前的工作提出了管理技术来缓解这种低效，但我们通过AgileWatts（AW）从根本上解决这一问题：一种针对数据中心服务器处理器优化的新型深度C状态架构，面向延迟敏感型应用。AW基于三个关键思想。第一，AW通过在CPU核内精心分布的中粒度电源门控实现，并在电源未门控域中保留上下文，消除了在深度空闲电源状态下关闭/开启核时保存/恢复核上下文（即微架构状态）的延迟开销。第二，AW通过保持L1/L2缓存内容电源未门控，消除了进入深度空闲电源状态时L1/L2缓存的刷新延迟开销（几十微秒）。最小控制逻辑也保持电源未门控，以无缝服务缓存一致性流量（即监听）。AW在缓存中实现睡眠模式以降低缓存泄漏功耗，并将核电压降至最低工作电压水平，以最小化电源未门控域的泄漏功耗。第三，使用最先进的节能全数字锁相环（ADPLL）时钟发生器，AW在空闲状态期间保持PLL激活并锁定，以可忽略的功耗代价进一步节省宝贵的唤醒延迟微秒。我们使用针对Intel Skylake服务器校准的精确模拟器进行评估，结果显示AW将Memcached的能耗降低高达71%（平均35%），性能下降最多1%。
英文摘要：
User-facing applications running in modern datacenters exhibit irregular request patterns and are implemented using a multitude of services with tight latency requirements. These characteristics render ineffective existing energy conserving techniques when processors are idle due to the long transition time from a deep idle power state (C-state). While prior works propose management techniques to mitigate this inefficiency, we tackle it at its root with AgileWatts (AW): a new deep C-state architecture optimized for datacenter server processors targeting latency-sensitive applications. AW is based on three key ideas. First, AW eliminates the latency overhead of saving/restoring the core context (i.e., micro-architectural state) when powering-off/-on the core in a deep idle power state by i) implementing medium-grained power-gates, carefully distributed across the CPU core, and ii) retaining context in the power-ungated domain. Second, AW eliminates the flush latency overhead (several tens of microseconds) of the L1/L2 caches when entering a deep idle power state by keeping L1/L2 cache content power-ungated. A minimal control logic also remains power-ungated to serve cache coherence traffic (i.e., snoops) seamlessly. AW implements sleep-mode in caches to reduce caches leakage power consumption and lowers a core voltage to the minimum operational voltage level to minimize the leakage power of the power-ungated domain. Third, using a state-of-the-art power efficient all-digital phase-locked loop (ADPLL) clock generator, AW keeps the PLL active and locked during the idle state, further cutting precious microseconds of wake-up latency at a negligible power cost. Our evaluation with an accurate simulator calibrated against an Intel Skylake server shows that AW reduces the energy consumption of Memcached by up to 71% (35% on average) with up to 1% performance degradation.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
