Puppeteer：一种基于随机森林的存储层次结构硬件预取器管理器。
Puppeteer: A Random Forest-based Manager for Hardware Prefetchers across the Memory Hierarchy
摘要：
多年来，处理器吞吐量稳步增长。然而，内存吞吐量并没有以相同的速度增加，这导致了内存墙问题，进而增加了有效和理论峰值处理器性能之间的差距。为了解决这个问题，在数据/指令预取器设计领域已经有了大量的工作。广义地说，预取器预测未来的数据/指令地址访问，并主动地在存储层次结构中获取数据/指令，目的是降低数据/指令访问延迟。为此，在存储层次结构的每个级别部署一个或多个预取器，但是通常，每个预取器被隔离地设计，而不全面考虑系统中的其他预取器。因此，各个预取器并不总是相互补充，这导致较低的平均性能增益和/或许多负异常值。在这项工作中，我们提出Puppeteer，这是一个硬件预取器管理器，使用一套随机森林回归器，以确定在运行时的预取器应在存储层次结构中的每个级别上，这样的预取器相互补充，我们减少了数据/指令访问延迟。与没有预取器的设计相比，使用Puppeteer，我们在1个核心（1C）中将IPC提高了46.0%，在4个核心（4C）中提高了25.8%，在8个核心（8 C）处理器中提高了11.9%，这些跟踪来自SPEC 2017，SPEC 2006和云套件，开销约为10 KB。此外，我们还将负离群值的数量减少了89%以上，并且与最先进的技术相比，最坏情况下的负离群值的性能损失从25%减少到仅5%。
英文摘要：
Over the years, processor throughput has steadily increased. However, the memory throughput has not increased at the same rate, which has led to the memory wall problem in turn increasing the gap between effective and theoretical peak processor performance. To cope with this, there has been an abundance of work in the area of data/instruction prefetcher designs. Broadly, prefetchers predict future data/instruction address accesses and proactively fetch data/instructions in the memory hierarchy with the goal of lowering data/instruction access latency. To this end, one or more prefetchers are deployed at each level of the memory hierarchy, but typically, each prefetcher gets designed in isolation without comprehensively accounting for other prefetchers in the system. As a result, individual prefetchers do not always complement each other, and that leads to lower average performance gains and/or many negative outliers. In this work, we propose Puppeteer, which is a hardware prefetcher manager that uses a suite of random forest regressors to determine at runtime which prefetcher should be ON at each level in the memory hierarchy, such that the prefetchers complement each other and we reduce the data/instruction access latency. Compared to a design with no prefetchers, using Puppeteer we improve IPC by 46.0% in 1 Core (1C), 25.8% in 4 Core (4C), and 11.9% in 8 Core (8C) processors on average across traces generated from SPEC2017, SPEC2006, and Cloud suites with ~10KB overhead. Moreover, we also reduce the number of negative outliers by over 89%, and the performance loss of the worst-case negative outlier from 25% to only 5% compared to the state-of-the-art.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
