更好地利用C-可测性和双射性的可测阵列乘法器
Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity
摘要：
本文提出了一种可测试设计（DFT）结构，用于快速和可扩展的阵列乘法器（MULT）测试。无论MULT的大小，我们提出的可测试架构，在原有的架构没有重大变化，只需要五个测试向量。结合C-可测性、双射性和确定性三种测试模式生成方法，实现了测试模式生成。实验结果表明，100%的故障覆盖率为单一的固定故障。所提出的方法需要较小的可测性硬件插入到乘法器与额外的延迟和面积开销小于0.5%的64位乘法器。
英文摘要：
This paper presents a design for test (DFT)architecture for fast and scalable testing of array multipliers (MULTs). Regardless of the MULT size, our proposed testable architecture, without major changes in the original architecture, requires only five test vectors. Test pattern generation (TPG) is done by combining C-testability, bijectivity and deterministic TPG methods. Experimental results show 100% fault coverage for single stuck-at faults. The proposed method requires minor testability hardware insertion into the multiplier with extra delay and area overhead of less than 0.5% for a 64-bit multiplier.
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