arXivDaily arXiv每日学术速递 周一至周五更新
arXiv周末暂无论文更新,休息一下吧,周末愉快~~
arXiv 2201.10632cs.LO
收藏

同步数字逻辑系统的高级描述与验证框架

A Framework for the High-Level Specification and Verification of Synchronous Digital Logic Systems

Nick Mertin, K. Ritsuka, Karen Rudie

摘要:

本文提出了一种语法模型,用于描述具有复杂输入/输出接口的有限状态同步数字逻辑系统,该接口控制不透明计算元素之间的数据流,并用于组成兼容系统以形成没有输入或输出的闭环系统。该模型改进了现有的类似模型,采用一种新颖的方法来指定输入和输出端口,这种方法是均匀和对称的。一个自动机模型也提出了编码任意的计算过程,并提出了一个算法来生成一个自动机表示的闭环系统。使用的自动机模型,对所需的行为规范,编码为闭环系统的相似性方面的一组计算执行的闭环系统的时间不可知验证的问题,被证明是可判定的。模型和现实世界的实现系统之间的关系进行了讨论。

英文摘要:

A syntactic model is presented for the specification of finite-state synchronous digital logic systems with complex input/output interfaces, which control the flow of data between opaque computational elements, and for the composition of compatible systems to form closed-loop systems with no inputs or outputs. This model improves upon similar existing models with a novel approach to specifying input and output ports in a way which is uniform and symmetric. An automaton model is also presented for encoding arbitrary computational processes, and an algorithm is presented to generate an automaton representation of a closed-loop system. Using the automaton model, the problem of timing-agnostic verification of closed-loop systems against a desired behavioural specification, encoded as the similarity of closed-loop systems in terms of the set of computations performed, is shown to be decidable. The relationship between the models and real-world implementations of systems is discussed.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

↑