低硬件消耗、分辨率可配置的格雷码振荡器时间数字转换器，采用16 nm、20 nm和28 nm FPGA实现
Low hardware consumption, resolution-configurable Gray code oscillator time-to-digital converters implemented in 16nm, 20nm and 28nm FPGAs
摘要：
介绍了一种基于Xilinx 16 nm UltraScale+、20 nm UltraScale和28 nm Virtex-7现场可编程门阵列（FPGA）的低硬件功耗、分辨率可配置、自动校准格雷码振荡器时间数字转换器（TDC）。本文提出的TDC有几个创新点：1）采样矩阵，以提高分辨率。2)一种虚拟面元标定方法，实现分辨率配置和自动标定。3)在标准FPGA器件中实现的VADS 2000。我们在所有三个FPGA中实现并评估了16通道TDC系统。UltraScale+版本实现了20.97 ps的最佳分辨率（最低有效位，LSB）和0.09 LSB平均峰峰值差分线性度（DNLpk-pk）。UltraScale和Virtex-7版本的最佳分辨率分别为36.01 ps（平均DNLpk-pk为0.10 LSB）和34.84 ps（平均DNLpk-pk为0.08 LSB）。
英文摘要：
This paper presents a low hardware consumption, resolution-configurable, automatically calibrating Gray code oscillator time-to-digital converter (TDC) in Xilinx 16nm UltraScale+, 20nm UltraScale and 28nm Virtex-7 field-programmable gate arrays (FPGAs). The proposed TDC has several innovations: 1) a sampling matrix to improve the resolution. 2) a virtual bin calibration method (VBCM) to realize resolution configuration and automatic calibration. 3) a hardware implementation of the VBCM in standard FPGA devices. We implemented and evaluated a 16-channel TDC system in all three FPGAs. The UltraScale+ version achieved the best resolution (least significant bit, LSB) of 20.97 ps with 0.09 LSB averaged peak-peak differential linearity (DNLpk-pk). The UltraScale and Virtex-7 versions achieved the best resolutions of 36.01 ps with 0.10 LSB averaged DNLpk-pk and 34.84 ps with 0.08 LSB averaged DNLpk-pk, respectively.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
