arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2201.06398cs.DCcs.AI

Efficient Data-Plane Memory Scheduling for In-Network Aggregation

iSING Lab, Hong Kong University of Science and Technology(香港科技大学 iSING 实验室);Harvard University(哈佛大学);Intel, Barefoot Switch Division(英特尔 Barefoot 交换机部门);Peking University(北京大学)

Hao Wang, Yuxuan Qin, ChonLam Lao, Yanfang Le, Wenfei Wu, Kai Chen

英文摘要:

As the scale of distributed training grows, communication becomes a bottleneck. To accelerate the communication, recent works introduce In-Network Aggregation (INA), which moves the gradients summation into network middle-boxes, e.g., programmable switches to reduce the traffic volume. However, switch memory is scarce compared to the volume of gradients transmitted in distributed training. Although literature applies methods like pool-based streaming or dynamic sharing to tackle the mismatch, switch memory is still a potential performance bottleneck. Furthermore, we observe the under-utilization of switch memory due to the synchronization requirement for aggregator deallocation in recent works. To improve the switch memory utilization, we propose ESA, an $\underline{E}$fficient Switch Memory $\underline{S}$cheduler for In-Network $\underline{A}$ggregation. At its cores, ESA enforces the preemptive aggregator allocation primitive and introduces priority scheduling at the data-plane, which improves the switch memory utilization and average job completion time (JCT). Experiments show that ESA can improve the average JCT by up to $1.35\times$.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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