Oblivious routing has a long history in both the theory and practice of networking. In this work we initiate the formal study of oblivious routing in the context of reconfigurable networks, a new architecture that has recently come to the fore in datacenter networking. These networks allow a rapidly changing bounded-degree pattern of interconnections between nodes, but the network topology and the selection of routing paths must both be oblivious to the traffic demand matrix. Our focus is on the trade-off between maximizing throughput and minimizing latency in these networks. For every constant throughput rate, we characterize (up to a constant factor) the minimum latency achievable by an oblivious reconfigurable network design that satisfies the given throughput guarantee. The trade-off between these two objectives turns out to be surprisingly subtle: the curve depicting it has an unexpected scalloped shape reflecting the fact that load-balancing becomes more difficult when the average length of routing paths is not an integer because equalizing all the path lengths is not possible. The proof of our lower bound uses LP duality to verify that Valiant load balancing is the most efficient oblivious routing scheme when used in combination with an optimally-designed reconfigurable network topology. The proof of our upper bound uses an algebraic construction in which the network nodes are identified with vectors over a finite field, the network topology is described by either the elementary basis or a sequence of Vandermonde matrices, and routing paths are constructed by selecting columns of these matrices to yield the appropriate mixture of path lengths within the shortest possible time interval.
Optimal Probabilistic Ring Exploration by Asynchronous Oblivious Robots
INSTITUT NATIONAL DE RECHERCHE EN INFORMATIQUE ET EN AUTOMATIQUE(法国国家信息与自动化研究所);VERIMAG UMR 5104(VERIMAG实验室(法国国家科研中心联合研究单位5104));Université Joseph Fourier(约瑟夫·傅里叶大学);INRIA(法国国家信息与自动化研究所);LIP UMR 5668(LIP实验室(法国国家科研中心联合研究单位5668));Université de Lyon(里昂大学);ENS Lyon(里昂高等师范学院);Université Pierre et Marie Curie - Paris 6(巴黎第六大学(皮埃尔和玛丽·居里大学));LIP6(LIP6实验室)
Efficient Tree Layout in a Multilevel Memory Hierarchy
我们考虑的问题,布局一棵树与固定的父/子结构的层次存储器。我们的目标是最大限度地减少预期数量的块传输搜索期间沿根到叶路径,叶上的概率分布。这个问题以前被Gil和Itai考虑过,他们在块传输大小B已知的情况下开发了最优但速度较慢的算法。我们提出了更快的,但近似算法相同的问题,最快的算法运行在线性时间,并产生一个解决方案,是在一个附加常数的最佳。此外,我们将展示如何扩展任何近似最优算法的缓存不经意设置中的块传输大小是未知的算法。缓存无关布局的查询性能是在一个恒定的因素的查询性能的最佳已知块大小的布局。计算缓存无关布局只需要在数学上多次调用已知块大小的布局算法;特别是,缓存无关布局可以在O(N lg N)时间内计算,其中N是节点数。最后,我们分析了两个贪婪的策略,并表明,他们有一个性能比之间的Omega(lg B / lg lg B)和O(lg B)的最佳布局相比。
Stony Brook University(石溪大学);Tokutek, Inc.(Tokutek公司);Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology(麻省理工学院计算机科学与人工智能实验室);University of Southern California(南加州大学);Akamai Technologies, Inc.(Akamai科技公司);Boston University(波士顿大学)