Xar-Trek：FPGA和异构ISA CPU之间的运行时间执行迁移
Xar-Trek: Run-time Execution Migration among FPGAs and Heterogeneous-ISA CPUs
摘要：
数据中心服务器的异构性越来越大：从x86主机CPU，到ARM或RISC-V CPU（在SSD/SSD中），再到FPGA。以前的工作已经证明，在运行时间跨异构ISA CPU迁移应用程序执行可以产生显着的性能和能量增益，相对较少的程序员工作。然而，在这种情况下，FPGA往往被忽视：使用FPGA的硬件加速涉及静态实现选定的应用程序功能，这阻碍了动态和透明的迁移。我们提出Xar-Trek，一个新的编译器和运行时间软件框架，克服了这一限制。Xar-Trek为多个CPU ISA编译应用程序，并选择应用程序功能在FPGA上加速，允许在运行时间在异构ISA CPU和FPGA之间执行迁移。Xar-Trek的运行时间监控服务器工作负载，并根据调度策略将应用程序功能迁移到FPGA或异构ISA CPU。我们开发了一个启发式的政策，使用应用程序的工作负载配置文件，使调度决策。我们在配备x86-64服务器CPU、ARM 64服务器CPU和Alveo加速卡的系统上进行的评估显示，与无迁移基线相比，性能提高了88%-1%。
英文摘要：
Datacenter servers are increasingly heterogeneous: from x86 host CPUs, to ARM or RISC-V CPUs in NICs/SSDs, to FPGAs. Previous works have demonstrated that migrating application execution at run-time across heterogeneous-ISA CPUs can yield significant performance and energy gains, with relatively little programmer effort. However, FPGAs have often been overlooked in that context: hardware acceleration using FPGAs involves statically implementing select application functions, which prohibits dynamic and transparent migration. We present Xar-Trek, a new compiler and run-time software framework that overcomes this limitation. Xar-Trek compiles an application for several CPU ISAs and select application functions for acceleration on an FPGA, allowing execution migration between heterogeneous-ISA CPUs and FPGAs at run-time. Xar-Trek's run-time monitors server workloads and migrates application functions to an FPGA or to heterogeneous-ISA CPUs based on a scheduling policy. We develop a heuristic policy that uses application workload profiles to make scheduling decisions. Our evaluations conducted on a system with x86-64 server CPUs, ARM64 server CPUs, and an Alveo accelerator card reveal 88%-1% performance gains over no-migration baselines.
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