利用存储器子区域邻接性为高吞吐量处理器实现大范围TLB
Enabling Large-Reach TLBs for High-Throughput Processors by Exploiting Memory Subregion Contiguity
摘要：
加速器（如GPU）已成为满足未来性能需求的趋势，并且越来越多地采用在CPU和GPU之间共享相同的虚拟内存空间以简化编程。然而，作为虚拟内存关键技术的地址转换，正逐渐成为制约GPU性能的瓶颈。在GPU中，由于SIMT执行模型，单个TLB未命中可能会使数百个线程停止，从而显著降低性能。通过实际系统分析，我们观察到操作系统显示出先进的连续性（例如，数百个连续页面），并且具有高级连续性的更大的存储器区域倾向于随着工作集的增加而被分配。利用观察结果，我们提出了MESC来提高GPU的翻译效率。MESC的关键思想是将虚拟内存空间中的每个大页面帧（2MB大小）划分为具有固定大小的内存子区域（即，64个4KB页面），并将子区域和大页面帧的邻接信息存储在L2PTE中。使用MESC，多达512个页面的地址转换可以合并到单个TLB条目中，而不需要改变存储器分配策略（即，请求分页）和对大页面的支持。在实验结果中，MESC实现了77.2%的性能提高和76.4%的动态翻译能量减少敏感的工作负载。
英文摘要：
Accelerators, like GPUs, have become a trend to deliver future performance desire, and sharing the same virtual memory space between CPUs and GPUs is increasingly adopted to simplify programming. However, address translation, which is the key factor of virtual memory, is becoming the bottleneck of performance for GPUs. In GPUs, a single TLB miss can stall hundreds of threads due to the SIMT execute model, degrading performance dramatically. Through real system analysis, we observe that the OS shows an advanced contiguity (e.g., hundreds of contiguous pages), and more large memory regions with advanced contiguity tend to be allocated with the increase of working sets. Leveraging the observation, we propose MESC to improve the translation efficiency for GPUs. The key idea of MESC is to divide each large page frame (2MB size) in virtual memory space into memory subregions with fixed size (i.e., 64 4KB pages), and store the contiguity information of subregions and large page frames in L2PTEs. With MESC, address translations of up to 512 pages can be coalesced into single TLB entry, without the needs of changing memory allocation policy (i.e., demand paging) and the support of large pages. In the experimental results, MESC achieves 77.2% performance improvement and 76.4% reduction in dynamic translation energy for translation-sensitive workloads.
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