Posit算法的精度与效率
The Accuracy and Efficiency of Posit Arithmetic
摘要：
出于越来越多的兴趣，在数字格式，在本文中，我们评估的准确性和效率，与传统的IEEE 754 32位浮点（FP 32）算法相比，数字运算。我们首先设计并实现了一个Posit算术单元（PAU），称为POSAR，具有灵活的位大小的算法，适用于可以以节省芯片面积来换取精度的应用程序。接下来，我们使用一系列基准测试来分析POSAR的准确性和效率，包括数学计算、ML内核、NAS并行基准测试（NPB）和Cifar-10 CNN。该分析是在我们的POSAR集成到RISC-V Rocket Chip内核中的实现上完成的，并与Rocket Chip基于IEEE 754的浮点单元（FPU）进行了比较。我们的分析表明，POSAR可以优于FPU，但结果并不壮观。对于NPB来说，32位FPGA实现了比FP 32更好的精度，并将执行效率提高了2%。然而，与FPU相比，具有32位FPGA的POSAR需要多30%的FPGA资源。对于经典的ML算法，我们发现8位的假设不适合取代FP 32，因为它们表现出低精度，导致错误的结果。相反，16位SDRAM在精度和效率方面提供了最佳选择。例如，在Cifar-10 CNN上，16位FPGA实现了与FP 32相同的Top-1精度，加速比为18%。
英文摘要：
Motivated by the increasing interest in the posit numeric format, in this paper we evaluate the accuracy and efficiency of posit arithmetic in contrast to the traditional IEEE 754 32-bit floating-point (FP32) arithmetic. We first design and implement a Posit Arithmetic Unit (PAU), called POSAR, with flexible bit-sized arithmetic suitable for applications that can trade accuracy for savings in chip area. Next, we analyze the accuracy and efficiency of POSAR with a series of benchmarks including mathematical computations, ML kernels, NAS Parallel Benchmarks (NPB), and Cifar-10 CNN. This analysis is done on our implementation of POSAR integrated into a RISC-V Rocket Chip core in comparison with the IEEE 754-based Floting Point Unit (FPU) of Rocket Chip. Our analysis shows that POSAR can outperform the FPU, but the results are not spectacular. For NPB, 32-bit posit achieves better accuracy than FP32 and improves the execution by up to 2%. However, POSAR with 32-bit posit needs 30% more FPGA resources compared to the FPU. For classic ML algorithms, we find that 8-bit posits are not suitable to replace FP32 because they exhibit low accuracy leading to wrong results. Instead, 16-bit posit offers the best option in terms of accuracy and efficiency. For example, 16-bit posit achieves the same Top-1 accuracy as FP32 on a Cifar-10 CNN with a speedup of 18%.
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