基于多片谐振器时钟分配网络的片间同步通信
Synchronous Chip-to-Chip Communication with a Multi-Chip Resonator Clock Distribution Network
摘要：
超导数字电路是构建高能效、高计算密度的封装级集成系统的一种很有前途的方法。在这样的系统中，安装在多芯片模块（MCM）上的芯片之间的数据链路的性能是性能的关键驱动因素。在这项工作中，我们报告了一个同步的数据链路，使用互易量子逻辑（RQL），使芯片上的谐振时钟分布和MCM载体。简单的物理链路只有四个约瑟夫森结和3 fJ/位耗散，包括300 W/W的冷却开销。该驱动器产生35 GHz模拟带宽的信号，并通过20 $Ω$ Nb无源传输线（PTL）连接到单端接收器。为了验证这一联系，我们设计、制造并测试了两个32 $\times$ 32 mm $^2$ MCM，其中8个5 $\times$ 5 mm $^2$芯片串联连接并由曲折时钟供电，以及4个10个$\times$ 10 mm $^2$芯片由2 GHz谐振时钟供电。曲折时钟MCM验证了数据链路组件的性能，并实现了5.4 dB的交流偏置裕度，相对于单个芯片测试没有退化。谐振器MCM验证芯片之间的同步，两个芯片之间的实测交流偏置裕度高达4.8 dB。谐振器MCM能够为四个芯片上的400万个约瑟夫森结电路供电，预计串行数据速率为10 Gbps。
英文摘要：
Superconducting digital circuits are a promising approach to build packaged-level integrated systems with high energy-efficiency and computational density. In such systems, performance of the data link between chips mounted on a multi-chip module (MCM) is a critical driver of performance. In this work we report a synchronous data link using Reciprocal Quantum Logic (RQL) enabled by resonant clock distribution on the chip and on the MCM carrier. The simple physical link has only four Josephson junctions and 3 fJ/bit dissipation, including a 300 W/W cooling overhead. The driver produces a signal with 35\,GHz analog bandwidth and connects to a single-ended receiver via 20 $Ω$ Nb Passive Transmission Line (PTL). To validate this link, we have designed, fabricated and tested two 32$\times$32 mm$^2$ MCMs with eight 5$\times$5 mm$^2$ chips connected serially and powered with a meander clock, and with four 10$\times$10 mm$^2$ chips powered with a 2 GHz resonant clock. The meander clock MCM validates performance of the data link components, and achieved 5.4 dB AC bias margin with no degradation relative to individual chip test. The resonator MCM validates synchronization between chips, with a measured AC bias margin up to 4.8 dB between two chips. The resonator MCM is capable of powering circuits of 4 million Josephson junctions across the four chips with a projected 10 Gbps serial data rate.
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