arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2108.13871cs.DCcs.SYeess.SY
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为具有替代实现的类型化DAG任务构建时间触发调度

Building Time-Triggered Schedules for typed-DAG Tasks with alternative implementations

Houssam-Eddine Zahaf, Nicola Capodieci

摘要:

像图像处理、自动驾驶等硬实时系统需要增加经典多核平台无法提供的计算能力的需求,以满足其时序约束。异构指令集架构(ISA)平台允许加速专用核(例如GPU、DSP、ASIC)等上的实时工作负载,并且适合于这些应用。此外,这些平台提供了更大的设计选择,因为给定的功能可以实现到几种类型的计算元件上。最近提出了HPC-DAG(异构并行有向无环图)任务模型,用于捕获异构平台上的实时工作负载执行。它表达了ISA的异构性,以及硬件加速器的一些特定特性,如没有抢占或昂贵的抢占,替代实现和在线条件执行。在本文中,我们提出了一个时间表调度方法来分配和调度一组HPC-DAG任务到一组异构的核心,通过平均线性规划(ILP)。通过逐步探索设计空间,我们的设计允许处理资源的异质性,在线执行成本和更快的求解时间

英文摘要:

Hard real-time systems like image processing, autonomous driving, etc. require an increasing need of computational power that classical multi-core platforms can not provide, to fulfill with their timing constraints. Heterogeneous Instruction Set Architecture (ISA) platforms allow accelerating real-time workloads on application-specific cores (e.g. GPU, DSP, ASICs) etc. and are suitable for these applications. In addition, these platforms provide larger design choices as a given functionnality can be implemented onto several types of compute elements. HPC-DAG (Heterogeneous Parallel Directed Acyclic Graph) task model has been recently proposed to capture real-time workload execution on heterogeneous platforms. It expresses the ISA heterogeneity, and some specific characteristics of hardware accelerators, as the absence of preemption or costly preemption, alternative implementations and on-line conditional execution. In this paper, we propose a time-table scheduling approach to allocate and schedule a set of HPC-DAG tasks onto a set of heterogeneous cores, by the mean Integer Linear Programming (ILP). Our design allows to handle heterogeniety of resources, on-line execution costs, and a faster solving time, by exploring gradually the design space

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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