具有最小加法器的无乘法器二阶IIR滤波器的硬件设计
Hardware-aware Design of Multiplierless Second-Order IIR Filters with Minimum Adders
摘要：
在这项工作中，我们最佳地解决了问题的无乘法器设计的二阶无限脉冲响应滤波器的加法器的数量最少。给定频率规格，我们设计了一个稳定的直接形式的滤波器与硬件感知的定点系数，产生最小数量的加法器时，取代所有的乘法位移位和加法。通常独立进行的系数设计、量化和实现现在被聚集到一个全局优化问题中，通过整数线性规划建模，并使用通用求解器有效地求解。我们保证频域规格和稳定性，这与最佳的加法器数量一起将显着简化滤波器设计者的设计空间探索。在FloPoCo IP核生成器中实现最佳滤波器，并为现场可编程门阵列进行合成。相对于最先进的三步滤波器设计方法，我们的一步设计方法实现了，平均而言，减少42%的查找表的数量和21%的延迟改善。
英文摘要：
In this work, we optimally solve the problem of multiplierless design of second-order Infinite Impulse Response filters with minimum number of adders. Given a frequency specification, we design a stable direct form filter with hardware-aware fixed-point coefficients that yielding minimal number of adders when replacing all the multiplications by bit shifts and additions. The coefficient design, quantization and implementation, typically conducted independently, are now gathered into one global optimization problem, modeled through integer linear programming and efficiently solved using generic solvers. We guarantee the frequency-domain specifications and stability, which together with optimal number of adders will significantly simplify design-space exploration for filter designers. The optimal filters are implemented within the FloPoCo IP core generator and synthesized for Field Programmable Gate Arrays. With respect to state-of-the-art three-step filter design methods, our one-step design approach achieves, on average, 42% reduction in the number of lookup tables and 21% improvement in delay.
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