Compute RAM：适用于DL优化FPGA的自适应计算和存储块
Compute RAMs: Adaptable Compute and Storage Blocks for DL-Optimized FPGAs
摘要：
当前FPGA的可配置构建块-逻辑块（LB）、数字信号处理（DSP）片和块RAM（BRAM）-使其成为快速变化的深度学习（DL）世界的高效硬件加速器。这些模块之间的通信通过由遍布FPGA的交换元件组成的互连结构进行。本文提出了一种新的块-计算RAM。计算RAM通过在一个块中组合计算和存储能力来提供高度并行处理的存储器内处理（PIM）。计算RAM可以像现有的FPGA块一样集成在FPGA结构中，并提供两种可以动态选择的操作模式（存储或计算）。它们通过减少数据移动来降低功耗，提供适应性高的精度支持，并增加有效的片内内存带宽。计算RAM还有助于提高FPGA的计算密度。在我们对多个数据精度（int 4，int 8和bfloat 16）的加法，乘法和点积运算的评估中，我们观察到平均节省了80%的能耗，并且执行时间从20%到80%不等。添加计算RAM也可以使非DL应用受益，并使FPGA更高效，灵活和高性能的加速器。
英文摘要：
The configurable building blocks of current FPGAs -- Logic blocks (LBs), Digital Signal Processing (DSP) slices, and Block RAMs (BRAMs) -- make them efficient hardware accelerators for the rapid-changing world of Deep Learning (DL). Communication between these blocks happens through an interconnect fabric consisting of switching elements spread throughout the FPGA. In this paper, a new block, Compute RAM, is proposed. Compute RAMs provide highly-parallel processing-in-memory (PIM) by combining computation and storage capabilities in one block. Compute RAMs can be integrated in the FPGA fabric just like the existing FPGA blocks and provide two modes of operation (storage or compute) that can be dynamically chosen. They reduce power consumption by reducing data movement, provide adaptable precision support, and increase the effective on-chip memory bandwidth. Compute RAMs also help increase the compute density of FPGAs. In our evaluation of addition, multiplication and dot-product operations across multiple data precisions (int4, int8 and bfloat16), we observe an average savings of 80% in energy consumption, and an improvement in execution time ranging from 20% to 80%. Adding Compute RAMs can benefit non-DL applications as well, and make FPGAs more efficient, flexible, and performant accelerators.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
