MELOPPR：高存储效率低延迟个性化PageRank的软硬件协同设计
MELOPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank
摘要：
个性化PageRank（PPR）是一种从源节点评估周围节点重要性的图算法。PPR广泛应用于社交网络相关的应用，如推荐系统，需要实时响应（延迟），以获得更好的用户体验。现有的工作要么集中在算法优化，以提高精度，而忽略了硬件实现或集中在分布式全局图形处理的大规模系统，以提高吞吐量，而不是响应时间。在边缘设备上使用紧凑的内存预算优化低延迟本地PPR算法仍然未被探索。在这项工作中，我们提出了一个内存高效，低延迟的PPR解决方案，即MeLoPPR，大大降低了内存需求和延迟和精度之间的灵活权衡。MeLoPPR由阶段分解和线性分解组成，利用节点得分的稀疏性：通过阶段分解和线性分解，MeLoPPR将大图上的计算分解为一组更小的子图，大大节省了计算内存;通过稀疏性利用，MeLoPPR选择对精度贡献最大的子图，减少所需的计算量。此外，通过软件/硬件协同设计，我们提出了一个硬件实现的混合CPU和FPGA加速平台，进一步加快子图计算。我们评估建议MeLoPPR内存受限的设备，包括个人笔记本电脑和Xilinx Kintex-7 KC 705 FPGA使用六个真实世界的图形。首先，MeLoPPR在CPU上节省了1.5倍至13.4倍的内存，在FPGA上节省了73倍至8699倍的内存。其次，MeLoPPR允许在精度和执行时间之间灵活权衡：当精度为80%时，CPU上的加速比高达15倍，FPGA上的加速比高达707倍;当精度为90%左右时，FPGA上的加速比高达70倍。
英文摘要：
Personalized PageRank (PPR) is a graph algorithm that evaluates the importance of the surrounding nodes from a source node. Widely used in social network related applications such as recommender systems, PPR requires real-time responses (latency) for a better user experience. Existing works either focus on algorithmic optimization for improving precision while neglecting hardware implementations or focus on distributed global graph processing on large-scale systems for improving throughput rather than response time. Optimizing low-latency local PPR algorithm with a tight memory budget on edge devices remains unexplored. In this work, we propose a memory-efficient, low-latency PPR solution, namely MeLoPPR, with largely reduced memory requirement and a flexible trade-off between latency and precision. MeLoPPR is composed of stage decomposition and linear decomposition and exploits the node score sparsity: Through stage and linear decomposition, MeLoPPR breaks the computation on a large graph into a set of smaller sub-graphs, that significantly saves the computation memory; Through sparsity exploitation, MeLoPPR selectively chooses the sub-graphs that contribute the most to the precision to reduce the required computation. In addition, through software/hardware co-design, we propose a hardware implementation on a hybrid CPU and FPGA accelerating platform, that further speeds up the sub-graph computation. We evaluate the proposed MeLoPPR on memory-constrained devices including a personal laptop and Xilinx Kintex-7 KC705 FPGA using six real-world graphs. First, MeLoPPR demonstrates significant memory saving by 1.5x to 13.4x on CPU and 73x to 8699x on FPGA. Second, MeLoPPR allows flexible trade-offs between precision and execution time: when the precision is 80%, the speedup on CPU is up to 15x and up to 707x on FPGA; when the precision is around 90%, the speedup is up to 70x on FPGA.
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