CodeAPeel：一种面向计算机体系结构课程的集成化分层学习技术
CodeAPeel: An Integrated and Layered Learning Technology For Computer Architecture Courses
摘要：
本文介绍了一种通用的，多层次的技术，以帮助支持教学和学习核心计算机体系结构的概念。这种称为CodeAPeel的技术已经以一种特定的形式实现，通过全面模拟其提取-解码-执行周期以及其CPU寄存器、RAM、VRAM、STACK存储器、各种控制寄存器和图形屏幕的行为，来描述通用指令集体系结构的编译器、汇编和机器层中的指令处理。与大多数模拟真实处理器（如MIPS或RISC-V）的教学CPU模拟器不同，CodeAPeel被设计和实现为通用RISC指令集架构模拟器，具有标量和矢量指令，以提供Flynn对SISD和SIMD处理器的分类所描述的双模处理器模拟器。操作的矢量化内置在CodeAPeel的指令库中，使得使用强大的矢量指令模拟此类处理器变得简单。
英文摘要：
This paper introduces a versatile, multi-layered technology to help support teaching and learning core computer architecture concepts. This technology, called CodeAPeel is already implemented in one particular form to describe instruction processing in compiler, assembly, and machine layers of a generic instruction set architecture by a comprehensive simulation of its fetch-decode-execute cycle as well as animation of the behavior of its CPU registers, RAM, VRAM, STACK memories, various control registers, and graphics screen. Unlike most educational CPU simulators that simulate a real processor such as MIPS or RISC-V, CodeAPeel is designed and implemented as a generic RISC instruction set architecture simulator with both scalar and vector instructions to provide a dual-mode processor simulator as described by Flynn's classification of SISD and SIMD processors. Vectorization of operations is built into the instruction repertoire of CodeAPeel, making it straightforward to simulate such processors with powerful vector instructions.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
