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arXiv 2104.08378cs.LGcs.AIcs.AR
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加速稀疏深度神经网络

Accelerating Sparse Deep Neural Networks

NVIDIA(英伟达)

Asit Mishra, Jorge Albericio Latorre, Jeff Pool, Darko Stosic, Dusan Stosic, Ganesh Venkatesh, Chong Yu, Paulius Micikevicius

摘要:

随着神经网络模型规模的急剧增加,人们对减少其参数计数并加速其执行的各种技术也产生了兴趣。这个领域的一个活跃的研究领域是稀疏性-鼓励参数中的零值,然后可以从存储或计算中丢弃。虽然大多数研究都集中在高水平的稀疏性上,但在普遍保持模型准确性以及在现代矩阵数学硬件上实现显着加速方面存在挑战。为了使稀疏性的采用变得切实可行,NVIDIA Ampere GPU架构在其矩阵数学单元Tensor Cores中引入了稀疏性支持。我们介绍了稀疏张量核心的设计和行为,它利用了2:4(50%)的稀疏模式,使密集矩阵单元的数学吞吐量增加了一倍。我们还描述了一个简单的工作流程,用于训练网络,既满足2:4稀疏模式要求,又保持准确性,并在广泛的常见任务和模型架构上进行验证。此工作流程可以轻松准备准确的模型,以便在稀疏张量核心上进行高效部署。

英文摘要:

As neural network model sizes have dramatically increased, so has the interest in various techniques to reduce their parameter counts and accelerate their execution. An active area of research in this field is sparsity - encouraging zero values in parameters that can then be discarded from storage or computations. While most research focuses on high levels of sparsity, there are challenges in universally maintaining model accuracy as well as achieving significant speedups over modern matrix-math hardware. To make sparsity adoption practical, the NVIDIA Ampere GPU architecture introduces sparsity support in its matrix-math units, Tensor Cores. We present the design and behavior of Sparse Tensor Cores, which exploit a 2:4 (50%) sparsity pattern that leads to twice the math throughput of dense matrix units. We also describe a simple workflow for training networks that both satisfy 2:4 sparsity pattern requirements and maintain accuracy, verifying it on a wide range of common tasks and model architectures. This workflow makes it easy to prepare accurate models for efficient deployment on Sparse Tensor Cores.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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