arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2103.14007cs.LGcs.AR
收藏

为边缘设备启用前向传递增量训练

Enabling Incremental Training with Forward Pass for Edge Devices

Santa Clara University(圣克拉拉大学);Palo Alto Networks(帕洛阿尔托网络公司)

Dana AbdulQader, Shoba Krishnan, Claudionor N. Coelho

摘要:

深度神经网络(DNN)通常部署在存在于不断变化的环境中的终端设备上。为了使系统保持其准确性,关键是它能够通过重新训练网络的部分来适应变化和恢复。然而,终端设备具有有限的资源,使得在同一设备上进行训练具有挑战性。此外,由于反向传播算法,训练深度神经网络是存储器和计算密集型的。在本文中,我们介绍了一种方法,使用进化策略(ES),可以部分重新训练网络,使其能够适应变化和恢复后,发生错误。这种技术可以在仅推理的硬件上进行训练,而无需使用反向传播,并且资源开销最小。我们证明了我们的技术的能力,重新训练量化MNIST神经网络后,注入噪声的输入。此外,我们提出了所需的微体系结构,使HLS4ML(推理硬件架构)的培训,并在Verilog中实现它。我们综合我们的实现Xilinx Kintex超规模现场可编程门阵列(FPGA),导致不到1%的资源利用率所需的实施增量培训。

英文摘要:

Deep Neural Networks (DNNs) are commonly deployed on end devices that exist in constantly changing environments. In order for the system to maintain it's accuracy, it is critical that it is able to adapt to changes and recover by retraining parts of the network. However, end devices have limited resources making it challenging to train on the same device. Moreover, training deep neural networks is both memory and compute intensive due to the backpropagation algorithm. In this paper we introduce a method using evolutionary strategy (ES) that can partially retrain the network enabling it to adapt to changes and recover after an error has occurred. This technique enables training on an inference-only hardware without the need to use backpropagation and with minimal resource overhead. We demonstrate the ability of our technique to retrain a quantized MNIST neural network after injecting noise to the input. Furthermore, we present the micro-architecture required to enable training on HLS4ML (an inference hardware architecture) and implement it in Verilog. We synthesize our implementation for a Xilinx Kintex Ultrascale Field Programmable Gate Array (FPGA) resulting in less than 1% resource utilization required to implement the incremental training.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

↑