SU3_Bench on Xeon和可编程集成统一内存架构的性能优化
Performance Optimization of SU3_Bench on Xeon and Programmable Integrated Unified Memory Architecture
摘要：
SU3\_Bench是一个微基准测试，旨在使用一个简单但不平凡的数学内核来探索跨多个编程模型/方法的性能可移植性。这个内核已经从MILC晶格量子色动力学（LQCD）代码。SU3\_Bench受带宽限制，并生成常规计算和数据访问模式。因此，在大多数传统的基于CPU和GPU的系统上，其性能主要取决于可实现的内存带宽。虽然SU3\_Bench是一个简单的内核，但经验表明，它的微妙之处需要一定的调整才能实现给定编程模型和硬件的峰值性能，这使得性能可移植性具有挑战性。在本文中，我们将分享在最先进的Intel Xeon计算机上获得SU3\_Bench峰值性能所面临的一些挑战，这些挑战是由于变量定义的细微差别、编译器提供的默认构造函数的性质、对象创建时访问内存的方式以及NUMA对计算机的影响。我们将讨论如何通过\(2\times\)来解决这些挑战，以提高SU3\_Bench的性能，并与Github上的原始OpenMP实现进行比较。这为其他类似的内核提供了宝贵的经验。扩展性能可移植性方面，我们还展示了将SU3\_Bench移植到新的英特尔可编程集成统一内存架构（PIUMA）的早期结果，其特点是更平衡的浮点数与字节数比。本文表明，它不是通常的带宽或触发器，而是流水线吞吐量，决定SU3\_Bench的性能在PIUMA上。最后，我们将展示如何提高PIUMA的性能，以及与Xeon的性能相比如何，Xeon的每字节浮点数大约高出一个数量级。
英文摘要：
SU3\_Bench is a microbenchmark developed to explore performance portability across multiple programming models/methodologies using a simple, but nontrivial, mathematical kernel. This kernel has been derived from the MILC lattice quantum chromodynamics (LQCD) code. SU3\_Bench is bandwidth bound and generates regular compute and data access patterns. Therefore, on most traditional CPU and GPU-based systems, its performance is mainly determined by the achievable memory bandwidth. Although SU3\_Bench is a simple kernel, experience says its subtleties require a certain amount of tweaking to achieve peak performance for a given programming model and hardware, making performance portability challenging. In this paper, we share some of the challenges in obtaining the peak performance for SU3\_Bench on a state-of-the-art Intel Xeon machine, due to the nuances of variable definition, the nature of compiler-provided default constructors, how memory is accessed at object creation time, and the NUMA effects on the machine. We discuss how to tackle those challenges to improve SU3\_Bench's performance by \(2\times\) compared to the original OpenMP implementation available at Github. This provides a valuable lesson for other similar kernels. Expanding on the performance portability aspects, we also show early results obtained porting SU3\_Bench to the new Intel Programmable Integrated Unified Memory Architecture (PIUMA), characterized by a more balanced flops-to-byte ratio. This paper shows that it is not the usual bandwidth or flops, rather the pipeline throughput, that determines SU3\_Bench's performance on PIUMA. Finally, we show how to improve performance on PIUMA and how that compares with the performance on Xeon, which has around one order of magnitude more flops-per-byte.
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