模糊硬件类似软件
Fuzzing Hardware Like Software
摘要：
硬件缺陷是永久性的，也是潜在的：硬件一旦制造出来就无法修补，任何缺陷都可能破坏在上面执行的任何软件。因此，验证时间占主导地位的实施时间。硬件设计验证（DV）的黄金标准集中在两个极端：随机动态验证和形式化验证。两者都在努力根除复杂硬件中的微妙缺陷，这些缺陷通常表现为安全漏洞。随机验证的根本问题在于其无向性，这使得其效率低下，而形式化验证受到状态空间爆炸问题的约束，这使得其对复杂设计不可行。我们需要的是一个有方向的解决方案，但不受约束。而不是对现有的DV方法进行增量改进，我们利用现有的软件模糊器已经提供了这样的解决方案，并使其适应硬件DV的观察。具体来说，我们将RTL硬件转换为软件模型并模糊该模型。我们解决的主要挑战是如何最好地减轻硬件执行模型和软件执行模型之间的差异。这包括：1）如何表示测试用例，2）什么是崩溃的硬件等价物，3）什么是适当的覆盖度量，以及4）如何为硬件创建通用的模糊化工具。为了评估我们的方法，我们模糊四个IP块从谷歌的OpenTitan SoC。我们的实验表明，减少了两个数量级的运行时间，以实现有限状态机（FSM）覆盖传统的动态验证方案。此外，通过我们的设计不可知的线束，我们在四分之三的设计中实现了超过88%的HDL线覆盖率-即使没有任何初始种子。
英文摘要：
Hardware flaws are permanent and potent: hardware cannot be patched once fabricated, and any flaws may undermine any software executing on top. Consequently, verification time dominates implementation time. The gold standard in hardware Design Verification (DV) is concentrated at two extremes: random dynamic verification and formal verification. Both struggle to root out the subtle flaws in complex hardware that often manifest as security vulnerabilities. The root problem with random verification is its undirected nature, making it inefficient, while formal verification is constrained by the state-space explosion problem, making it infeasible against complex designs. What is needed is a solution that is directed, yet under-constrained. Instead of making incremental improvements to existing DV approaches, we leverage the observation that existing software fuzzers already provide such a solution, and adapt them for hardware DV. Specifically, we translate RTL hardware to a software model and fuzz that model. The central challenge we address is how best to mitigate the differences between the hardware execution model and software execution model. This includes: 1) how to represent test cases, 2) what is the hardware equivalent of a crash, 3) what is an appropriate coverage metric, and 4) how to create a general-purpose fuzzing harness for hardware. To evaluate our approach, we fuzz four IP blocks from Google's OpenTitan SoC. Our experiments reveal a two orders-of-magnitude reduction in run time to achieve Finite State Machine (FSM) coverage over traditional dynamic verification schemes. Moreover, with our design-agnostic harness, we achieve over 88% HDL line coverage in three out of four of our designs -- even without any initial seeds.
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