竞争优势：在资源有限的边缘计算应用中，FPGA能否在DCNN推理加速方面击败GPU？
A Competitive Edge: Can FPGAs Beat GPUs at DCNN Inference Acceleration in Resource-Limited Edge Computing Applications?
摘要：
当作为生成模型进行训练时，深度学习算法在涉及高维数据的任务（如图像去噪和超分辨率）上表现出卓越的性能。在一个由移动和边缘设备主导的日益互联的世界中，对这些算法在嵌入式平台上本地运行的需求激增。FPGA凭借其可重编程性和低功耗特性，是这些边缘计算应用的理想候选者。因此，我们设计了一个时空并行的硬件架构，能够加速一个去卷积算法优化的电源效率的推理资源有限的FPGA。我们提出了这种基于FPGA的加速器，用于低功耗边缘计算应用中的解卷积神经网络（DCNN）推理。为此，我们开发了系统地利用微观建筑创新，设计空间探索和统计分析的方法。使用Xilinx PYNQ-Z2 FPGA，我们利用我们的架构来加速使用Wasserstein GAN框架在MNIST和CelebA数据集上训练的两个DCNN的推理。在这些网络上，与NVIDIA Jetson TX 1边缘计算GPU相比，我们的FPGA设计实现了更高的吞吐量与功率比，同时降低了运行间变化。
英文摘要：
When trained as generative models, Deep Learning algorithms have shown exceptional performance on tasks involving high dimensional data such as image denoising and super-resolution. In an increasingly connected world dominated by mobile and edge devices, there is surging demand for these algorithms to run locally on embedded platforms. FPGAs, by virtue of their reprogrammability and low-power characteristics, are ideal candidates for these edge computing applications. As such, we design a spatio-temporally parallelized hardware architecture capable of accelerating a deconvolution algorithm optimized for power-efficient inference on a resource-limited FPGA. We propose this FPGA-based accelerator to be used for Deconvolutional Neural Network (DCNN) inference in low-power edge computing applications. To this end, we develop methods that systematically exploit micro-architectural innovations, design space exploration, and statistical analysis. Using a Xilinx PYNQ-Z2 FPGA, we leverage our architecture to accelerate inference for two DCNNs trained on the MNIST and CelebA datasets using the Wasserstein GAN framework. On these networks, our FPGA design achieves a higher throughput to power ratio with lower run-to-run variation when compared to the NVIDIA Jetson TX1 edge computing GPU.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
