MF-Net：基于内存数据转换和无乘法运算的多位精度推理的内存计算SRAM
MF-Net: Compute-In-Memory SRAM for Multibit Precision Inference using Memory-immersed Data Conversion and Multiplication-free Operators
摘要：
我们提出了一种用于深度神经网络（DNN）的内存计算推理的协同设计方法。我们使用基于ell_1范数的无乘法函数逼近器以及自适应处理阵列和计算流程。使用该方法，我们克服了SRAM内DNN处理的当前技术中的许多缺陷，诸如在每个操作SRAM行/列处需要数模转换器（DAC）、需要高精度模数转换器（ADC）、对多位精度权重的有限支持以及有限的向量规模并行性。我们的自适应实现可无缝扩展到多位精度权重，不需要DAC，并且可以轻松扩展到更高的向量规模并行性。我们还提出了一种SRAM浸没式逐次逼近型ADC（SA-ADC），利用SRAM阵列位线的寄生电容作为容性DAC。由于SA-ADC的主要面积开销来自其容性DAC，因此通过利用SRAM阵列的固有寄生，我们的方法允许SRAM内SA-ADC的低面积实现。我们的8 $\times$ 62 SRAM宏需要一个5位ADC，在45 nm CMOS工艺下实现了$\sim$ 105 tera/s/W（TOPS/W）的运算速度，并具有8位输入/权重处理能力。
英文摘要：
We propose a co-design approach for compute-in-memory inference for deep neural networks (DNN). We use multiplication-free function approximators based on ell_1 norm along with a co-adapted processing array and compute flow. Using the approach, we overcame many deficiencies in the current art of in-SRAM DNN processing such as the need for digital-to-analog converters (DACs) at each operating SRAM row/column, the need for high precision analog-to-digital converters (ADCs), limited support for multi-bit precision weights, and limited vector-scale parallelism. Our co-adapted implementation seamlessly extends to multi-bit precision weights, it doesn't require DACs, and it easily extends to higher vector-scale parallelism. We also propose an SRAM-immersed successive approximation ADC (SA-ADC), where we exploit the parasitic capacitance of bit lines of SRAM array as a capacitive DAC. Since the dominant area overhead in SA-ADC comes due to its capacitive DAC, by exploiting the intrinsic parasitic of SRAM array, our approach allows low area implementation of within-SRAM SA-ADC. Our 8$\times$62 SRAM macro, which requires a 5-bit ADC, achieves $\sim$105 tera operations per second per Watt (TOPS/W) with 8-bit input/weight processing at 45 nm CMOS.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
