通过优化读取延迟减少固态驱动器Read延迟（扩展摘要）
Reducing Solid-State Drive Read Latency by Optimizing Read-Retry (Extended Abstract)
摘要：
具有高级多级单元技术的3D NAND闪存提供高存储密度，但是由于大量的读取重试操作而遭受显著的性能降级。虽然读重试机制对于确保现代NAND闪存的可靠性是必不可少的，但是它可以通过引入利用调整的读参考电压值再次读取目标页的多个重试步骤来显著增加SSD的读延迟。通过对160个真实3D NAND闪存芯片的读取机制和严格表征的详细分析，我们发现了通过利用现代NAND闪存SSD中广泛采用的两个先进功能来减少读取重试延迟的新机会：1）CACHE READ命令和2）强大的ECC引擎。首先，我们可以使用高级CACHE READ命令来减少读取重试延迟，该命令允许NAND闪存芯片以流水线方式执行连续读取。其次，在最后的重试步骤中存在大的ECC能力裕度，其可用于减少芯片级读取延迟。基于我们的新发现，我们开发了两种新的技术，有效地减少了读重试延迟：1）流水线读缓存（PR $^2$）和2）自适应读缓存（AR $^2$）。PR $^2$通过使用CACHE READ命令对连续重试步骤进行流水线处理，减少了读重试操作的延迟。AR $^2$可根据决定ECC能力裕度的当前工作条件动态减少芯片级读取延迟，从而缩短每个重试步骤的延迟。我们使用十二个真实世界的工作负载进行的评估表明，我们的建议将SSD的响应时间提高了31.5%（平均17%），超过了最先进的基线，只需对SSD控制器进行很小的更改。
英文摘要：
3D NAND flash memory with advanced multi-level cell techniques provides high storage density, but suffers from significant performance degradation due to a large number of read-retry operations. Although the read-retry mechanism is essential to ensuring the reliability of modern NAND flash memory, it can significantly increase the read latency of an SSD by introducing multiple retry steps that read the target page again with adjusted read-reference voltage values. Through a detailed analysis of the read mechanism and rigorous characterization of 160 real 3D NAND flash memory chips, we find new opportunities to reduce the read-retry latency by exploiting two advanced features widely adopted in modern NAND flash-based SSDs: 1) the CACHE READ command and 2) strong ECC engine. First, we can reduce the read-retry latency using the advanced CACHE READ command that allows a NAND flash chip to perform consecutive reads in a pipelined manner. Second, there exists a large ECC-capability margin in the final retry step that can be used for reducing the chip-level read latency. Based on our new findings, we develop two new techniques that effectively reduce the read-retry latency: 1) Pipelined Read-Retry (PR$^2$) and 2) Adaptive Read-Retry (AR$^2$). PR$^2$ reduces the latency of a read-retry operation by pipelining consecutive retry steps using the CACHE READ command. AR$^2$ shortens the latency of each retry step by dynamically reducing the chip-level read latency depending on the current operating conditions that determine the ECC-capability margin. Our evaluation using twelve real-world workloads shows that our proposal improves SSD response time by up to 31.5% (17% on average) over a state-of-the-art baseline with only small changes to the SSD controller.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
