构造加法器和AND-OR路径的深度最佳电路
Constructing Depth-Optimum Circuits for Adders and AND-OR Paths
摘要：
我们研究的基本问题，构建深度优化电路的二进制加法。更确切地说，在文献中，我们考虑以下问题：给定辅助输入$t_0, \dotsc, t_{m-1}$，所谓的生成和传播信号，在基{AND 2，OR 2}上构造深度最优电路，计算$n$位加法器的所有$n$进位位，其中$m=2n-1$。实际上，进位位是AND-OR路径，即，形式为$t_0 \lor ( t_1 \land (t_2 \lor ( \dots t_{m-1}) \dots ))$的布尔函数。经典的方法构造所谓的前缀电路，其不实现竞争深度。例如，Kogge和Stone的流行构造只是一个$2$近似。任何前缀电路的深度的下限是$1.44 \log_2 m$ + const，而最近的非前缀电路的深度是$\log_2 m$ + $\log_2 \log_2 m$ + const。然而，不知道这些多项式时间方法中的任何一种是否达到了所有$m$的最佳深度。我们提出了一个新的指数时间算法解决问题的最优。运行时间为$\mathcal O(2.45^m)$的先前最佳精确算法仅适用于$m \leq 29$。我们的算法是显着更快：我们实现了$\mathcal O(2.02^m)$的运行时间，并采用先进的修剪策略，以提高实际运行时间显着。这使我们能够计算所有$m \leq 64$的最佳电路。结合这些计算结果与新的理论见解，我们得出的最佳深度$2^k$位加法器电路的所有$k \leq 13$，以前只知道$k \leq 4$。事实上，我们解决了一个更普遍的问题发生在VLSI设计：$delay$优化的$generalization$的AND-或路径，其中AND和OR不一定交替。我们的算法产生于我们的新的结构定理，其特点是延迟最佳的广义与或路径电路。
英文摘要：
We examine the fundamental problem of constructing depth-optimum circuits for binary addition. More precisely, as in literature, we consider the following problem: Given auxiliary inputs $t_0, \dotsc, t_{m-1}$, so-called generate and propagate signals, construct a depth-optimum circuit over the basis {AND2, OR2} computing all $n$ carry bits of an $n$-bit adder, where $m=2n-1$. In fact, carry bits are AND-OR paths, i.e., Boolean functions of the form $t_0 \lor ( t_1 \land (t_2 \lor ( \dots t_{m-1}) \dots ))$. Classical approaches construct so-called prefix circuits which do not achieve a competitive depth. For instance, the popular construction by Kogge and Stone is only a $2$-approximation. A lower bound on the depth of any prefix circuit is $1.44 \log_2 m$ + const, while recent non-prefix circuits have a depth of $\log_2 m$ + $\log_2 \log_2 m$ + const. However, it is unknown whether any of these polynomial-time approaches achieves the optimum depth for all $m$. We present a new exponential-time algorithm solving the problem optimally. The previously best exact algorithm with a running time of $\mathcal O(2.45^m)$ is viable only for $m \leq 29$. Our algorithm is significantly faster: We achieve a running time of $\mathcal O(2.02^m)$ and apply sophisticated pruning strategies to improve practical running times dramatically. This allows us to compute optimum circuits for all $m \leq 64$. Combining these computational results with new theoretical insights, we derive the optimum depths of $2^k$-bit adder circuits for all $k \leq 13$, previously known only for $k \leq 4$. In fact, we solve a more general problem occurring in VLSI design: $delay$ optimization of a $generalization$ of AND-OR paths where AND and OR do not necessarily alternate. Our algorithm arises from our new structure theorem which characterizes delay-optimum generalized AND-OR path circuits.
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