A Single-Cycle MLP Classifier Using Analog MRAM-based Neurons and Synapses

SOT-MRAM based Sigmoidal Neuron for Neuromorphic Architectures

In this paper, the intrinsic physical characteristics of spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM) devices are leveraged to realize sigmoidal neurons in neuromorphic architectures. Performance comparisons with the previous power- and area-efficient sigmoidal neuron circuits exhibit 74x and 12x reduction in power-area-product values for the proposed SOT-MRAM based neuron. To verify the functionally of the proposed neuron within larger scale designs, we have implemented a circuit realization of a 784x16x10 SOT-MRAM based multiplayer perceptron (MLP) for MNIST pattern r…

MRAM-based Analog Sigmoid Function for In-memory Computing

We propose an analog implementation of the transcendental activation function leveraging two spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and a CMOS inverter. The proposed analog neuron circuit consumes 1.8-27x less power, and occupies 2.5-4931x smaller area, compared to the state-of-the-art analog and digital implementations. Moreover, the developed neuron can be readily integrated with memristive crossbars without requiring any intermediate signal conversion units. The architecture-level analyses show that a fully-analog in-memory computing (IMC) circuit that us…

An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices

In this paper, we develop an in-memory analog computing (IMAC) architecture realizing both synaptic behavior and activation functions within non-volatile memory arrays. Spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices are leveraged to realize sigmoidal neurons as well as binarized synapses. First, it is shown the proposed IMAC architecture can be utilized to realize a multilayer perceptron (MLP) classifier achieving orders of magnitude performance improvement compared to previous mixed-signal and digital implementations. Next, a heterogeneous mixed-signal and mixed-pr…

一种用于低功耗模拟SNN推理且具有eNVM突触的可调谐、多用途28nm FD-SOI交叉开关输出电路

A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses

本文提出一种28nm FD-SOI模拟SNN交叉开关输出电路协同设计方法，集成可调电流衰减器与漏积分发放神经元，支持多种eNVM突触，并通过仿真与实验数据评估神经元扇入能力。

基于元神经细胞自动机的架构泛化

Architecture Generalization with MetaNCA

研究受生物神经元启发，引入MetaNCA框架学习局部规则自组织神经网络权重。提出新颖权重变换器架构，经训练的规则网络无需反向传播生成多样任务网络，在MNIST和CIFAR - 100上实验，证明其能生成权重并泛化到未见架构。