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arXiv 2012.02453cs.LGcs.AR
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使用机器学习优化设计验证:开源解决方案

Optimising Design Verification Using Machine Learning: An Open Source Solution

National Institute of Technology Karnataka, Surathkal(卡纳塔克国家理工学院苏拉特卡尔校区);Birla Institute of Technology and Science, Pilani(贝拉理工学院皮拉尼校区)

B. Samhita Varambally, Naman Sehgal

摘要:

随着集成电路复杂度的不断提高,设计验证已经成为ASIC设计流程中最耗时的部分。SoC设计周期的近70%用于验证。测试所有极端情况的最常用方法是使用约束随机验证。随机刺激是为了击中所有可能的组合,并彻底测试设计。然而,这种方法通常需要大量的人力专业知识来达到所有的角落情况。本文提出了一种使用机器学习来生成输入刺激的替代方案。这将允许以较少的人为干预更快地彻底验证设计。此外,建议使用开源验证环境“Cocotb”。基于Python,它简单,直观,并为机器学习应用程序提供了大量的函数库。这使得它比使用传统硬件验证语言(如System Verilog或Specman E)的笨重方法更方便。

英文摘要:

With the complexity of Integrated Circuits increasing, design verification has become the most time consuming part of the ASIC design flow. Nearly 70% of the SoC design cycle is consumed by verification. The most commonly used approach to test all corner cases is through the use of Constrained Random Verification. Random stimulus is given in order to hit all possible combinations and test the design thoroughly. However, this approach often requires significant human expertise to reach all corner cases. This paper presents an alternative using Machine Learning to generate the input stimulus. This will allow for faster thorough verification of the design with less human intervention. Furthermore, it is proposed to use the open source verification environment 'Cocotb'. Based on Python, it is simple, intuitive and has a vast library of functions for machine learning applications. This makes it more convenient to use than the bulkier approach using traditional Hardware Verification Languages such as System Verilog or Specman E.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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