Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra

SARIS：利用间接流寄存器加速高能效 RISC-V 计算集群上的模板计算

SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers

提出 SARIS 方法，通过寄存器映射间接流降低模板计算的地址与访存开销，并在 RISC-V 集群及众核扩展中验证其性能与能效收益。

Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores

Single-issue processor cores are very energy efficient but suffer from the von Neumann bottleneck, in that they must explicitly fetch and issue the loads/storse necessary to feed their ALU/FPU. Each instruction spent on moving data is a cycle not spent on computation, limiting ALU/FPU utilization to 33% on reductions. We propose "Stream Semantic Registers" to boost utilization and increase energy efficiency. SSR is a lightweight, non-invasive RISC-V ISA extension which implicitly encodes memory accesses as register reads/writes, eliminating a large number of loads/stores. We implement the prop…

稀疏流语义寄存器：一种加速通用稀疏线性代数的轻量级 ISA 扩展

Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra

本文提出轻量级 RISC-V ISA 扩展，以流式间接寻址、交集和并集原语支持 CSR/CSF 等格式的单侧与双侧稀疏运算，在极小面积开销下显著提升性能、能效和 FPU 利用率。

IntersectX: An Efficient Accelerator for Graph Mining

Graph pattern mining applications try to find all embeddings that match specific patterns. Compared to the traditional graph computation, graph mining applications are computation-intensive. The state-of-the-art method, pattern enumeration, constructs the embeddings that match the pattern. The key operation -- intersection -- of two edge lists, poses challenges to conventional architectures and requires substantial execution time. In this paper, we propose IntersectX, a vertically designed accelerator for pattern enumeration with stream instruction set extension and architectural supports base…

AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer Architecture

Convolutional neural network (CNN) accelerators are being widely used for their efficiency, but they require a large amount of memory, leading to the use of a slow and power consuming external memory. This paper exploits two schemes to reduce the required memory amount and ultimately to implement a CNN of reasonable performance only with on-chip memory of a practical device like a low-end FPGA. To reduce the memory amount of the intermediate data, a stream-based line-buffer architecture and a dataflow for the architecture are proposed instead of the conventional frame-based architecture, where…

解决面向流应用的向量处理器中的内存带宽可扩展性问题

Addressing memory bandwidth scalability in vector processors for streaming applications

针对AI/ML模型与数据集增长带来的内存带宽瓶颈，本文提出含三级片上存储器、超宽寄存器与数据混洗器的扩展内存层次架构，经CNN应用验证，其性能优于GPU及传统脉动阵列、向量处理器类加速器。