图形处理加速器的内存访问模式研究
Exploring Memory Access Patterns for Graph Processing Accelerators
摘要：
商业和技术的最新趋势（例如，机器学习、社会网络分析）受益于在数据库和数据科学平台中存储和处理越来越多的图形结构数据。作为具有可定制的存储层次结构的图形处理的加速器的FPGA承诺解决由传统硬件上固有的不规则存储器访问模式（例如，CPU）。然而，开发这样的硬件加速器仍然是耗时且困难的，并且基准测试是非标准化的，这阻碍了对存储器访问模式变化的影响的理解和图形处理加速器的系统工程。在这项工作中，我们提出了一个模拟环境的基础上模拟他们的内存访问模式的图形处理加速器的分析。此外，我们评估了我们的方法在两个国家的最先进的FPGA图形处理加速器，并显示再现性，可比性，以及缩短开发过程的例子。在FPGA等加速器硬件上不实现周期精确的内部数据流可显著缩短实现时间，提高基准参数透明度，并允许比较图形处理方法。
英文摘要：
Recent trends in business and technology (e.g., machine learning, social network analysis) benefit from storing and processing growing amounts of graph-structured data in databases and data science platforms. FPGAs as accelerators for graph processing with a customizable memory hierarchy promise solving performance problems caused by inherent irregular memory access patterns on traditional hardware (e.g., CPU). However, developing such hardware accelerators is yet time-consuming and difficult and benchmarking is non-standardized, hindering comprehension of the impact of memory access pattern changes and systematic engineering of graph processing accelerators. In this work, we propose a simulation environment for the analysis of graph processing accelerators based on simulating their memory access patterns. Further, we evaluate our approach on two state-of-the-art FPGA graph processing accelerators and show reproducibility, comparablity, as well as the shortened development process by an example. Not implementing the cycle-accurate internal data flow on accelerator hardware like FPGAs significantly reduces the implementation time, increases the benchmark parameter transparency, and allows comparison of graph processing approaches.
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