无同步器数字链路控制器
Synchronizer-Free Digital Link Controller
摘要：
这项工作提出了两个独立的时钟域之间的生产者-消费者的链接。该链路允许通过对由控制器电路操纵的生产者和消费者域的时钟频率进行轻微调整来实现无亚稳态、低延迟、高吞吐量的通信。任何这样的控制器都不能确定性地避免、检测或解决亚稳态。通常，这是由同步器解决的，在控制回路中产生更大的死区时间。我们遵循Friedrichs等人（TC 2018）的方法，他们提出了含亚稳态的电路。其结果是一个简单的控制电路，可以成为亚稳态，但确定性地避免缓冲器欠载或上溢。更具体地说，控制器输出可能变得亚稳态，但这可能只影响特定界限内的振荡器速度。相反，通信保证保持无亚稳态。我们正式证明正确的生产者-消费者的链接和可能的实现，只有很小的开销。与SPICE模拟建议的实施，我们进一步证实了我们的主张。模拟使用65 nm工艺，运行频率约为2GHz。
英文摘要：
This work presents a producer-consumer link between two independent clock domains. The link allows for metastability-free, low-latency, high-throughput communication by slight adjustments to the clock frequencies of the producer and consumer domains steered by a controller circuit. Any such controller cannot deterministically avoid, detect, nor resolve metastability. Typically, this is addressed by synchronizers, incurring a larger dead time in the control loop. We follow the approach of Friedrichs et al. (TC 2018) who proposed metastability-containing circuits. The result is a simple control circuit that may become metastable, yet deterministically avoids buffer underrun or overflow. More specifically, the controller output may become metastable, but this may only affect oscillator speeds within specific bounds. In contrast, communication is guaranteed to remain metastability-free. We formally prove correctness of the producer-consumer link and a possible implementation that has only small overhead. With SPICE simulations of the proposed implementation we further substantiate our claims. The simulation uses 65nm process running at roughly 2GHz.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
