用与或路径重构优化组合逻辑的延迟
Delay Optimization of Combinational Logic by And-Or Path Restructuring
摘要：
我们提出了一个动态规划算法，构造延迟优化电路交替与或路径与规定的输入到达时间。我们的算法实现了最知名的近似保证，并通过探索更大部分的解决方案空间，经验上优于早期的方法。我们的算法是一个新的定时优化框架，取代关键路线的任意长度的逻辑等价实现具有更少的延迟的核心。我们的框架允许在工业物理设计流程的后期步骤中修改关于网表的逻辑结构的早期决定。实验证明了我们的工具在7nm真实世界的实例的有效性。
英文摘要：
We propose a dynamic programming algorithm that constructs delay-optimized circuits for alternating And-Or paths with prescribed input arrival times. Our algorithm fulfills best-known approximation guarantees and empirically outperforms earlier methods by exploring a significantly larger portion of the solution space. Our algorithm is the core of a new timing optimization framework that replaces critical paths of arbitrary length by logically equivalent realizations with less delay. Our framework allows revising early decisions on the logical structure of the netlist in a late step of an industrial physical design flow. Experiments demonstrate the effectiveness of our tool on 7nm real-world instances.
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