FIGARO：通过细粒度的DRAM内数据重定位和缓存来提高系统性能
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching
摘要：
DRAM主存储器由于高访问延迟而成为许多应用的性能瓶颈。DRAM内缓存通过使用DRAM的小而快的区域来增加常规延迟DRAM来减轻这种延迟，这些区域用作DRAM的常规延迟区域中保存的数据的缓存。虽然有效的DRAM内高速缓存可以允许从快速DRAM区域服务大部分存储器请求，但是延迟节省通常受到用于将数据的副本重新定位到快速区域中和从快速区域重新定位出来的低效机制的阻碍。现有的DRAM内高速缓存具有两个低效率的来源：（1）数据重定位粒度是DRAM的整个多字节行;以及（2）因为重定位延迟随着慢区域与快区域之间的物理距离而增加，所以多个快区域在慢区域之间物理地交织以减少重定位延迟，从而导致增加的硬件面积和制造复杂性。我们提出了一个新的基板，FIGARO，使用现有的共享全局缓冲区的DRAM银行内的子阵列之间提供支持，在一个单一的高速缓存块的粒度跨子阵列的DRAM数据重新定位。FIGARO在DRAM组内具有与距离无关的延迟，并且避免了对DRAM的复杂修改。使用FIGARO，我们设计了一个细粒度的DRAM缓存称为FIGCache。FIGCache的关键思想是在DRAM的指定区域中仅缓存不同DRAM行的小的、频繁访问的部分。通过只缓存每行中预期在不久的将来会被访问的部分，我们可以将更多频繁访问的数据打包到FIGCache中，并且可以从DRAM中的额外行命中中受益。我们的评估表明，FIGCache将使用DDR4 DRAM的系统的平均性能提高了16.3%，并将8核工作负载的平均DRAM能耗降低了7.8%，超过了没有DRAM内缓存的传统系统。
英文摘要：
DRAM Main memory is a performance bottleneck for many applications due to the high access latency. In-DRAM caches work to mitigate this latency by augmenting regular-latency DRAM with small-but-fast regions of DRAM that serve as a cache for the data held in the regular-latency region of DRAM. While an effective in-DRAM cache can allow a large fraction of memory requests to be served from a fast DRAM region, the latency savings are often hindered by inefficient mechanisms for relocating copies of data into and out of the fast regions. Existing in-DRAM caches have two sources of inefficiency: (1) the data relocation granularity is an entire multi-kilobyte row of DRAM; and (2) because the relocation latency increases with the physical distance between the slow and fast regions, multiple fast regions are physically interleaved among slow regions to reduce the relocation latency, resulting in increased hardware area and manufacturing complexity. We propose a new substrate, FIGARO, that uses existing shared global buffers among subarrays within a DRAM bank to provide support for in-DRAM data relocation across subarrays at the granularity of a single cache block. FIGARO has a distance-independent latency within a DRAM bank, and avoids complex modifications to DRAM. Using FIGARO, we design a fine-grained in-DRAM cache called FIGCache. The key idea of FIGCache is to cache only small, frequently-accessed portions of different DRAM rows in a designated region of DRAM. By caching only the parts of each row that are expected to be accessed in the near future, we can pack more of the frequently-accessed data into FIGCache, and can benefit from additional row hits in DRAM. Our evaluations show that FIGCache improves the average performance of a system using DDR4 DRAM by 16.3% and reduces average DRAM energy consumption by 7.8% for 8-core workloads, over a conventional system without in-DRAM caching.
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