用于多层感知器的AutoML和FPGA协同设计
AutoML for Multilayer Perceptron and FPGA Co-design
摘要：
最先进的神经网络架构（NNA）的设计和硬件实现效率的挑战。在过去的几年里，这导致了自动神经结构搜索（NAS）工具的研究和开发的爆炸式增长。AutomML工具现在用于实现最先进的NNA设计，并尝试优化硬件使用和设计。最近在NNA自动设计方面的大部分研究都集中在卷积网络和图像识别上，忽略了数据中心工作量的重要部分是通用深度神经网络这一事实。在这项工作中，我们开发和测试了一个通用的多层感知器（MLP）流，可以将任意数据集作为输入，并自动生成优化的NNA和硬件设计。我们在六个基准上测试流。我们的研究结果表明，我们超过了目前公布的MLP精度结果的性能，并与非MLP为基础的结果具有竞争力。我们将通用和常见的GPU架构与我们的可扩展FPGA设计进行了比较，并表明我们可以为大多数数据集实现更高的效率和更高的吞吐量（每秒输出）。对精确网络和高性能硬件的设计空间的进一步深入了解通过将准确性与吞吐量、网络大小与准确性以及扩展到高性能设备相关联来展示协同设计的力量。
英文摘要：
State-of-the-art Neural Network Architectures (NNAs) are challenging to design and implement efficiently in hardware. In the past couple of years, this has led to an explosion in research and development of automatic Neural Architecture Search (NAS) tools. AutomML tools are now used to achieve state of the art NNA designs and attempt to optimize for hardware usage and design. Much of the recent research in the auto-design of NNAs has focused on convolution networks and image recognition, ignoring the fact that a significant part of the workload in data centers is general-purpose deep neural networks. In this work, we develop and test a general multilayer perceptron (MLP) flow that can take arbitrary datasets as input and automatically produce optimized NNAs and hardware designs. We test the flow on six benchmarks. Our results show we exceed the performance of currently published MLP accuracy results and are competitive with non-MLP based results. We compare general and common GPU architectures with our scalable FPGA design and show we can achieve higher efficiency and higher throughput (outputs per second) for the majority of datasets. Further insights into the design space for both accurate networks and high performing hardware shows the power of co-design by correlating accuracy versus throughput, network size versus accuracy, and scaling to high-performance devices.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
