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arXiv 2009.06119cs.ET
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MERAM:基于磁电场效应管的非易失性高速缓冲存储器

MERAM: Non-Volatile Cache Memory Based on Magneto-Electric FETs

Shaahin Angizi, Navid Khoshavi, Andrew Marshall, Peter Dowben, Deliang Fan

摘要:

磁电场效应晶体管(MEFET)是一种新型的后CMOS场效应晶体管,在逻辑和存储器应用中具有高速、低功耗的特点。在本文中,我们首次提出了一种非易失性2 T-1 MEFET存储器位单元与单独的读取和写入路径。我们表明,适当的协同设计在设备,单元和阵列级,这样的设计是一个有前途的候选人快速非易失性高速缓存存储器,称为MERAM。为了进一步评估其在存储器系统中的性能,我们首次基于实验校准的MEFET器件模型构建了一个器件到架构的跨层评估框架,以定量分析和基准测试所提出的MERAM设计与其他存储器技术,包括易失性存储器(即SRAM,eDRAM)和其他流行的非易失性新兴存储器(即ReRAM,STT-MRAM和SOT-MRAM)。实验结果表明,MERAM具有高的状态可重复性,检测电流相差近36倍。PARSEC基准测试套件的结果表明,作为L2缓存的替代方案,MERAM与典型的6 T SRAM和2 T SOT-MRAM平台相比,平均可将能量区域延迟(EAT)积分别降低约98%和约70%。

英文摘要:

Magneto-Electric FET (MEFET) is a recently developed post-CMOS FET, which offers intriguing characteristics for high speed and low-power design in both logic and memory applications. In this paper, for the first time, we propose a non-volatile 2T-1MEFET memory bit-cell with separate read and write paths. We show that with proper co-design at the device, cell and array levels, such a design is a promising candidate for fast non-volatile cache memory, termed as MERAM. To further evaluate its performance in memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework based on an experimentally-calibrated MEFET device model to quantitatively analyze and benchmark the proposed MERAM design with other memory technologies, including both volatile memory (i.e. SRAM, eDRAM) and other popular non-volatile emerging memory (i.e. ReRAM, STT-MRAM, and SOT-MRAM). The experiment results show that MERAM has a high state distinguishability with almost 36x magnitude difference in sense current. Results for the PARSEC benchmark suite indicate that as an L2 cache alternative, MERAM reduces Energy Area Latency (EAT) product on average by ~98\% and ~70\% compared with typical 6T SRAM and 2T SOT-MRAM platforms, respectively.

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