arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2009.01432cs.ARcs.LG
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FPGA动态功率在线监测的包围学习方法

An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power

Hong Kong University of Science and Technology(香港科技大学)

Zhe Lin, Sharad Sinha, Wei Zhang

摘要:

随着现场可编程门阵列在关键应用领域的普及,其功耗受到高度关注。在本文中,我们提出并评估了一个电源监控方案,能够准确地估计在细粒度的时间尺度的FPGA的运行时动态功率,以支持新兴的电源管理技术。特别是,我们描述了一种新的和专门的集成模型,可以分解成多个定制的基于决策树的基础学习器。为了辅助模型合成,提出了一种通用的计算机辅助设计流程来生成样本、选择特征、调整超参数和训练集成估计器。此外,给出了一种用于片上实时功率估计的训练集成估计器的硬件实现。在实验中,我们首先表明,一个单一的决策树模型可以实现预测误差在4.51%的商业门级功耗估计工具,这是2.41- 6.07倍,低于通常使用的线性模型提供。更重要的是,我们研究了额外的增益,使用建议的集成模型的推理精度。实验结果表明,集合监测方法可以进一步提高功率预测的准确性,最大误差为1.90%。此外,使用多达64个基本学习器的系综监控硬件的查找表(LUT)开销在目标FPGA的1.22%以内,表明其重量轻且可扩展的特性。

英文摘要:

As field-programmable gate arrays become prevalent in critical application domains, their power consumption is of high concern. In this paper, we present and evaluate a power monitoring scheme capable of accurately estimating the runtime dynamic power of FPGAs in a fine-grained timescale, in order to support emerging power management techniques. In particular, we describe a novel and specialized ensemble model which can be decomposed into multiple customized decision-tree-based base learners. To aid in model synthesis, a generic computer-aided design flow is proposed to generate samples, select features, tune hyperparameters and train the ensemble estimator. Besides this, a hardware realization of the trained ensemble estimator is presented for on-chip real-time power estimation. In the experiments, we first show that a single decision tree model can achieve prediction error within 4.51% of a commercial gate-level power estimation tool, which is 2.41--6.07x lower than provided by the commonly used linear model. More importantly, we study the extra gains in inference accuracy using the proposed ensemble model. Experimental results reveal that the ensemble monitoring method can further improve the accuracy of power predictions to within a maximum error of 1.90%. Moreover, the lookup table (LUT) overhead of the ensemble monitoring hardware employing up to 64 base learners is within 1.22% of the target FPGA, indicating its light-weight and scalable characteristics.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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