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arXiv 2008.11669cs.AR
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一种具有可调节被动神经元和位线权重映射的8位阻性存储器计算核

An 8-bit In Resistive Memory Computing Core with Regulated Passive Neuron and Bit Line Weight Mapping

Yewei Zhang, Kejie Huang, Rui Xiao, Haibin Shen

摘要:

人工智能(AI)和物联网(IoT)的快速发展增加了对低功耗和相对高处理速度设备的边缘计算的需求。基于电阻式非易失性存储器(NVM)的内存计算(CIM)方案在降低人工智能计算功耗方面显示出巨大的潜力。然而,非易失性存储器的设备不一致性可能显著地降低神经网络的性能。在本文中,我们提出了一个低功耗的电阻式RAM(RRAM)的CIM核,不仅实现了高的计算效率,但也大大提高了鲁棒性的位线调节器和位线权重映射算法。仿真结果表明,我们提出的8位CIM核的功耗仅为3.61mW(256*256)。CIM核心的SFDR和SNDR分别达到59.13 dB和46.13 dB。在ImageNet Large Scale Visual Recognition Competition 2012(ILSVRC 2012)中,AlexNet和VGG16在8位模式下的前1位准确率分别提高了2.46%和3.47%。

英文摘要:

The rapid development of Artificial Intelligence (AI) and Internet of Things (IoT) increases the requirement for edge computing with low power and relatively high processing speed devices. The Computing-In-Memory(CIM) schemes based on emerging resistive Non-Volatile Memory(NVM) show great potential in reducing the power consumption for AI computing. However, the device inconsistency of the non-volatile memory may significantly degenerate the performance of the neural network. In this paper, we propose a low power Resistive RAM (RRAM) based CIM core to not only achieve high computing efficiency but also greatly enhance the robustness by bit line regulator and bit line weight mapping algorithm. The simulation results show that the power consumption of our proposed 8-bit CIM core is only 3.61mW (256*256). The SFDR and SNDR of the CIM core achieve 59.13 dB and 46.13 dB, respectively. The proposed bit line weight mapping scheme improves the top-1 accuracy by 2.46% and 3.47% for AlexNet and VGG16 on ImageNet Large Scale Visual Recognition Competition 2012 (ILSVRC 2012) in 8-bit mode, respectively.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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