打破障碍：最大限度地提高内存中计算结构的阵列利用率
Breaking Barriers: Maximizing Array Utilization for Compute In-Memory Fabrics
摘要：
内存计算（CIM）是一种很有前途的技术，它可以最大限度地减少数据传输，这是大多数数据密集型应用程序的主要性能瓶颈和能源成本。这在加速机器学习应用的神经网络中得到了广泛的采用。利用具有诸如密集电阻随机存取存储器（RRAM）或相变随机存取存储器（PCRAM）之类的新兴非易失性存储器（eNVM）的交叉开关架构，可以实现各种形式的神经网络以大大降低功率并增加片上存储器容量。然而，内存计算在电路和设备层面都面临着自身的局限性。虽然使用交叉开关架构的存储器内计算可以大大减少数据传输，但这些大型固定权重矩阵的刚性性质丧失了传统CMOS和SRAM设计的灵活性。在这项工作中，我们探讨了不同的同步障碍，发生从CIM的约束。此外，我们提出了一个新的分配算法和数据流的基础上输入数据分布，以最大限度地提高利用率和性能的计算在内存为基础的设计。我们证明了一个7.47 $\times$的性能提高了一个天真的分配方法的CIM加速器上ResNet18。
英文摘要：
Compute in-memory (CIM) is a promising technique that minimizes data transport, the primary performance bottleneck and energy cost of most data intensive applications. This has found wide-spread adoption in accelerating neural networks for machine learning applications. Utilizing a crossbar architecture with emerging non-volatile memories (eNVM) such as dense resistive random access memory (RRAM) or phase change random access memory (PCRAM), various forms of neural networks can be implemented to greatly reduce power and increase on chip memory capacity. However, compute in-memory faces its own limitations at both the circuit and the device levels. Although compute in-memory using the crossbar architecture can greatly reduce data transport, the rigid nature of these large fixed weight matrices forfeits the flexibility of traditional CMOS and SRAM based designs. In this work, we explore the different synchronization barriers that occur from the CIM constraints. Furthermore, we propose a new allocation algorithm and data flow based on input data distributions to maximize utilization and performance for compute-in memory based designs. We demonstrate a 7.47$\times$ performance improvement over a naive allocation method for CIM accelerators on ResNet18.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
