采用面对面晶圆键合技术的3D堆叠高性能商用微处理器热分析
Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology
摘要：
3D集成技术在半导体行业中得到广泛采用，以抵消二维缩放的限制和放缓。高密度3D集成技术（例如，具有小于10 $μ$ m间距的面对面晶片接合）可实现使用所有3个维度设计SoC的新方法，例如跨多个3D层折叠微处理器设计。然而，由于功率密度的普遍增加，重叠的热热点在这种3D堆叠设计中可能是一个挑战。在这项工作中，我们进行了彻底的热仿真研究的签核质量的物理设计实现的一个国家的最先进的，高性能的，无序的微处理器上的7纳米工艺技术。微处理器的物理设计被划分并以2层、3D堆叠配置实现，其中逻辑块和存储器实例在单独的层中（逻辑存储器3D）。热仿真模型根据采用相同7nm工艺技术制造的高性能、基于CPU的2D SoC芯片的温度测量数据进行了校准。在各种工作负载条件下，不同的3D配置的热剖面进行了模拟和比较。我们发现，在最坏情况下的功耗指示工作负载下，在不考虑热影响的情况下堆叠3D微处理器设计可能会导致最高芯片温度比2D微处理器高出高达12°C。这种温度的增加将减少在需要调节之前可以运行功率密集型工作负载的时间量。然而，存储器上逻辑分区的3D CPU实现可以将这种温度增加减轻一半，这使得3D设计的温度仅比2D基线高6 $^\circ$ C。我们的结论是，使用热感知设计分区和改进的冷却技术可以克服与3D堆叠相关的热挑战。
英文摘要：
3D integration technologies are seeing widespread adoption in the semiconductor industry to offset the limitations and slowdown of two-dimensional scaling. High-density 3D integration techniques such as face-to-face wafer bonding with sub-10 $μ$m pitch can enable new ways of designing SoCs using all 3 dimensions, like folding a microprocessor design across multiple 3D tiers. However, overlapping thermal hotspots can be a challenge in such 3D stacked designs due to a general increase in power density. In this work, we perform a thorough thermal simulation study on sign-off quality physical design implementation of a state-of-the-art, high-performance, out-of-order microprocessor on a 7nm process technology. The physical design of the microprocessor is partitioned and implemented in a 2-tier, 3D stacked configuration with logic blocks and memory instances in separate tiers (logic-over-memory 3D). The thermal simulation model was calibrated to temperature measurement data from a high-performance, CPU-based 2D SoC chip fabricated on the same 7nm process technology. Thermal profiles of different 3D configurations under various workload conditions are simulated and compared. We find that stacking microprocessor designs in 3D without considering thermal implications can result in maximum die temperature up to 12°C higher than their 2D counterparts under the worst-case power-indicative workload. This increase in temperature would reduce the amount of time for which a power-intensive workload can be run before throttling is required. However, logic-over-memory partitioned 3D CPU implementation can mitigate this temperature increase by half, which makes the temperature of the 3D design only 6$^\circ$C higher than the 2D baseline. We conclude that using thermal aware design partitioning and improved cooling techniques can overcome the thermal challenges associated with 3D stacking.
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