arXiv 2007.103302020-07-20cs.LGcs.AR

SHEARer：基于软硬件多重近似的高效超维计算

SHEARer: Highly-Efficient Hyperdimensional Computing by Software-Hardware Enabled Multifold Approximation

UC San Diego（加州大学圣迭戈分校）

Behnam Khaleghi, Sahand Salamat, Anthony Thomas, Fatemeh Asgarinejad, Yeseong Kim, Tajana Rosing

备注：: A shorter version is accepted in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2020)

摘要：

超维计算（HD）是一种新兴的机器学习范式，它基于大脑对高维、分布式数据表示进行计算的证据。HD的主要操作是编码，通过将每个输入特征映射到超向量，将输入数据转移到超空间，伴随着所谓的捆绑过程，简单地将超向量相加以实现编码超向量。虽然HD的操作是高度并行化的，但大量的操作阻碍了HD在嵌入式领域的效率。在本文中，我们提出了SHEARer，一种算法硬件协同优化，以提高性能和能耗的HD计算。我们从一个谨慎的近似超向量的方案中获得了洞察力，由于HD固有的错误弹性，对精度的影响最小，同时为硬件优化提供了很高的前景。与以前的工作，产生编码超矢量在全精度，然后事后量化，我们计算的编码超矢量的近似方式，节省了大量的资源，但提供高精度。我们还提出了一种新的FPGA实现，实现了惊人的性能，通过大规模的并行低功耗。此外，我们开发了一个软件框架，使训练HD模型，通过模拟提出的近似编码。与使用实用机器学习数据集在Raspberry Pi 3（GeForce GTX 1080 Ti）上实现的最先进的编码方法相比，SHEARer的FPGA实现了104，904倍（15.7倍）的平均吞吐量提升和高达56，044倍（301倍）的节能。

英文摘要：

Hyperdimensional computing (HD) is an emerging paradigm for machine learning based on the evidence that the brain computes on high-dimensional, distributed, representations of data. The main operation of HD is encoding, which transfers the input data to hyperspace by mapping each input feature to a hypervector, accompanied by so-called bundling procedure that simply adds up the hypervectors to realize encoding hypervector. Although the operations of HD are highly parallelizable, the massive number of operations hampers the efficiency of HD in embedded domain. In this paper, we propose SHEARer, an algorithm-hardware co-optimization to improve the performance and energy consumption of HD computing. We gain insight from a prudent scheme of approximating the hypervectors that, thanks to inherent error resiliency of HD, has minimal impact on accuracy while provides high prospect for hardware optimization. In contrast to previous works that generate the encoding hypervectors in full precision and then ex-post quantizing, we compute the encoding hypervectors in an approximate manner that saves a significant amount of resources yet affords high accuracy. We also propose a novel FPGA implementation that achieves striking performance through massive parallelism with low power consumption. Moreover, we develop a software framework that enables training HD models by emulating the proposed approximate encodings. The FPGA implementation of SHEARer achieves an average throughput boost of 104,904x (15.7x) and energy savings of up to 56,044x (301x) compared to state-of-the-art encoding methods implemented on Raspberry Pi 3 (GeForce GTX 1080 Ti) using practical machine learning datasets.

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