eSampling：能量收集ADC
eSampling: Energy Harvesting ADCs
摘要：
模数转换器（ADC）允许使用数字硬件处理物理信号。转换中消耗的功率随着采样速率和量化分辨率的增加而增加，这在功率受限的系统中带来了重大挑战。常见的ADC架构基于采样保持（S/H）电路，其中仅在采样周期的一小部分内跟踪模拟信号。在本文中，我们提出了eSampling ADC的概念，它在信号未被跟踪的时间段内从模拟信号中获取能量。收集的能量可用于补充ADC本身，为零功耗和节能ADC铺平道路。我们分析了恢复采样信号的能力和收获的能量之间的权衡，并提供了根据精度和能量约束设置采样率的指导方针。我们的分析表明，每个样本高达12位的eSampling ADC可以采集带宽受限的模拟信号，从而可以完美地恢复这些信号，而无需外部电源供电。此外，我们的理论结果表明，eSampling ADC实际上可以通过收集比消耗更多的能量来节省功耗。为了验证eSampling ADC的可行性，我们提出了一种采用标准互补金属氧化物半导体（CMOS）65 nm工艺的电路级设计。在Cadence Virtuoso平台上设计了一个采样频率为40 MHz的eSampling 8位ADC。我们对带限信号进行奈奎斯特速率采样的实验研究表明，这种ADC确实能够在不影响精度的情况下，获得比模数转换期间消耗的更多的能量。
英文摘要：
Analog-to-digital converters (ADCs) allow physical signals to be processed using digital hardware. The power consumed in conversion grows with the sampling rate and quantization resolution, imposing a major challenge in power-limited systems. A common ADC architecture is based on sample-and-hold (S/H) circuits, where the analog signal is being tracked only for a fraction of the sampling period. In this paper, we propose the concept of eSampling ADCs, which harvest energy from the analog signal during the time periods where the signal is not being tracked. This harvested energy can be used to supplement the ADC itself, paving the way to the possibility of zero-power consumption and power-saving ADCs. We analyze the tradeoff between the ability to recover the sampled signal and the energy harvested, and provide guidelines for setting the sampling rate in the light of accuracy and energy constraints. Our analysis indicates that eSampling ADCs operating with up to 12 bits per sample can acquire bandlimited analog signals such that they can be perfectly recovered without requiring power from the external source. Furthermore, our theoretical results reveal that eSampling ADCs can in fact save power by harvesting more energy than they consume. To verify the feasibility of eSampling ADCs, we present a circuit-level design using standard complementary metal oxide semiconductor (CMOS) 65 nm technology. An eSampling 8-bit ADC which samples at 40 MHZ is designed on a Cadence Virtuoso platform. Our experimental study involving Nyquist rate sampling of bandlimited signals demonstrates that such ADCs are indeed capable of harvesting more energy than that spent during analog-to-digital conversion, without affecting the accuracy.
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